Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?(a) IEEE(b) RAPID(c) JEDEC(d) UNESCOThis question was addressed to me in an international level competition.The origin of the question is DRAM Refreshing Techniques topic in chapter Memory Systems of Embedded Systems

Which technology is standardized in DRAM for determining the maximum t

1.	Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?(a) IEEE(b) RAPID(c) JEDEC(d) UNESCOThis question was addressed to me in an international level competition.The origin of the question is DRAM Refreshing Techniques topic in chapter Memory Systems of Embedded Systems
Answer» Correct ANSWER is (c) JEDEC To ELABORATE: The maximum TIME interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the MANUFACTURER’s chip specification.

Discussion

No Comment Found

Related InterviewSolutions

Which writing mechanism forms the backbone of the bus snooping mechanism?(a) write-back(b) write-through(c) no caching of write cycles(d) write bufferI had been asked this question by my college director while I was bunking the class.The question is from Writing Scheme of Cache Memory in division Memory Systems of Embedded Systems
In which writing scheme does all the data writes go through to main memory and update the system and cache?(a) write-through(b) write-back(c) write buffering(d) no caching of writing cycleThe question was asked in an international level competition.I'd like to ask this question from Writing Scheme of Cache Memory topic in division Memory Systems of Embedded Systems
Which of the following protocol matches the MC68040?(a) MCM62486(b) US 5729504 A(c) HyperBus(d) MCM62940I have been asked this question in final exam.The question is from Burst Interfaces in division Memory Systems of Embedded Systems
How can gate delays be reduced?(a) synchronous memory(b) asynchronous memory(c) pseudo asynchronous memory(d) symmetrical memoryThis question was addressed to me in an interview for internship.I would like to ask this question from Burst Interfaces in chapter Memory Systems of Embedded Systems
What does MESI stand for?(a) modified exclusive stale invalid(b) modified exclusive shared invalid(c) modified exclusive system input(d) modifies embedded shared invalidThis question was posed to me in an interview for job.The above asked question is from Writing Scheme of Cache Memory in chapter Memory Systems of Embedded Systems
How does the memory management unit provide the protection?(a) disables the address translation(b) enables the address translation(c) wait for the address translation(d) remains unchangedI have been asked this question in class test.Asked question is from Memory Protection Unit topic in portion Memory Systems of Embedded Systems
Which of the following bits are used to control the cache behaviour?(a) cacheable bit(b) buffer bit(c) cacheable bit and buffer bit(d) cacheable bit, buffer bit and permission access bitThe question was posed to me during an interview for a job.I'd like to ask this question from Memory Protection Unit topic in chapter Memory Systems of Embedded Systems
How many regions are created by the memory range in the ARM architecture?(a) 4(b) 8(c) 16(d) 32The question was posed to me in quiz.The doubt is from Memory Protection Unit topic in chapter Memory Systems of Embedded Systems
How many bits does the memory region in the ARM memory protection unit have?(a) 1(b) 2(c) 3(d) 4This question was addressed to me in an online interview.I need to ask this question from Memory Protection Unit topic in chapter Memory Systems of Embedded Systems
Which of the following is the biggest challenge in the cache memory design?(a) delay(b) size(c) coherency(d) memory accessThe question was posed to me in class test.My query is from Writing Scheme of Cache Memory in division Memory Systems of Embedded Systems

Discussion

No Comment Found

Related InterviewSolutions

Reply to Comment