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The correct choice is (c) no caching of write cycles

The explanation: The no caching of write cycle SEEMS to be wasteful because it does not update the cache, and if any PREVIOUS data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this WRITING scheme forms the backbone of the bus SNOOPING system for the coherency issue.

The correct CHOICE is (a) write-through

To elaborate: There are different WRITING scheme in the CACHE memory which increases the cache efficiency and one such is the write-through in which all the data GO to the main memory and can update the system as well as the cache.

The correct OPTION is (d) MCM62940

The explanation is: The MCM62940 and MCM62486 are the specific PROTOCOLS developed by Motorola, in which the MCM62940 has an on-chip COUNTER which matches the wrap-around BURST interfacing of the MC68040.

Correct option is (a) synchronous MEMORY

To explain: The burst INTERFACED is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip LATCHES to REDUCE the gate DELAYS.

The correct option is (b) MODIFIED exclusive shared invalid

To explain I WOULD say: The MESI protocol supports a shared state which is a formal mechanism for CONTROLLING the cache coherency by using the BUS snooping techniques. MESI refers to the states that cached data can ACCESS. In MESI protocol, multiple processors can cache shared data.

Right choice is (a) disables the address translation

The best explanation: The MEMORY MANAGEMENT unit can be USED as a PROTECTION unit by disabling the address translation that is, the PHYSICAL address and the logical address are the same.

Correct choice is (c) cacheable bit and buffer bit

To EXPLAIN: The cacheable bit and the buffer bit are USED to CONTROL the behaviour of cache. Depending on the cacheable bit and the buffer bit, the memory access will complete successfully.

Correct option is (b) 8

The explanation is: The MEMORY protection unit in the ARM ARCHITECTURE divides the memory into eight separate regions. Each REGION can be small as well as big ranging from 4 Kbytes to 4 Gbytes.

The correct answer is (C) 3

The best I can explain: The MEMORY REGION possesses three bits which are the cacheable bit, bufferable bit and access PERMISSION bit.

Correct CHOICE is (c) coherency

To elaborate: The coherency is a major challenge in designing the cache memory. The cache has to be designed by SOLVING the problem of data coherency while REMAINING hardware and SOFTWARE compatible.

Right CHOICE is (B) fully ASSOCIATIVE CACHE

Easy explanation: A fully associative cache have a COMPARATOR for each entry so that all the entries can be tested simultaneously.

Correct answer is (b) write-back

For explanation: The cache write-back mechanism needs a BUS SNOOPING SYSTEM for the coherency. In this write-back scheme, the cache is UPDATED first and the main memory is not updated.

The correct answer is (c) 1

For EXPLANATION: The direct mapping cache have only one COMPARATOR so that only one location POSSIBLY have all the DATA irrespective of the cache size.

The correct option is (b) granularity

Easiest explanation: The granularity bit controls the resolution of the segmented MEMORY. When it is SET to LOGIC one, the resolution is 4 KB. When the granularity bit is set to logic ZERO, the resolution is 1 byte.

Right choice is (a) DEC Alpha

To explain: DEC Alpha DIVIDES its memory into 8KB PAGES whereas VAX is a small PAGE which is only 512 bytes in size. PowerPC pages are normally 4 KB and ARM is having 4 KB and 64 KB pages.

Right option is (B) BURST interfacing

The explanation: The burst interfaces reduces the clock CYCLES. For fetching four words with a three clock memory, it will take 12 clock cycle but in the burst interface, it will only take FIVE clocks to ACCESS the data.

Correct CHOICE is (b) cache COHERENCY

For explanation I would say: The problem of cache coherency lead to the formation of two STANDARD mechanisms called MESI and MEI PROTOCOL. MC88100 have MESI protocol and MC68040 USES an MEI protocol.

Right choice is (a) MC88100

To explain: The bus snooping MECHANISM uses a combination of cache tag STATUS, write policies and bus monitoring to ENSURE coherency. MC88100 or MC88200 uses bus snooping mechanism.

The correct choice is (c) n way set ASSOCIATIVE

To explain: Only one data can be accessed in direct mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as BUS thrashing which can be SOLVED by splitting up the caches so there are 2,4,..n possible entries AVAILABLE. The major advantage of the set associative cache is its capability to prevent the bus thrashing at the EXPENSE of hardware.

Right answer is (c) SRAM

For EXPLANATION I WOULD SAY: The BURST interface is ASSOCIATED with the static RAM.

The correct option is (B) harvard

The explanation is: The Harvard cache have a separate cache for the data and the instruction WHEREAS the UNIFIED cache has a same cache for the data and instructions.

The CORRECT ANSWER is (c) modified EXCLUSIVE invalid

The best explanation: MEI protocol is less complex and is EASY to IMPLEMENT. It does not allow shared state for the cache.

Correct CHOICE is (b) physical cache

Explanation: In the physical cache, the data is preserved within the cache because it does not flush out during the context switching but on the other HAND, the logical cache FLUSHES out the data and clear it during a context switching.

The correct choice is (d) direct mapping

The BEST I can explain: The direct mapping CACHE organization is simple from the hardware DESIGN aspects but it is inefficient in the SOFTWARE viewpoint.

Right answer is (c) dirty BIT

The explanation is: The dirty bit is said to be set if the processor MODIFIES its MEMORY. This bit indicates that the associative set of blocks REGARDING the memory is modified and has not yet saved to the STORAGE.

The correct CHOICE is (c) bus snooping

Explanation: There are four main writing scheme in the cache MEMORY which is, write-through, write-back, no CACHING of the write cycle and write BUFFER. All these writing schemes are designed for bus snooping which can reduce the coherency.

Correct choice is (a) write BUFFER

For EXPLANATION I would say: The write-buffer is slightly similar to the write-through MECHANISM in which data is written to the main memory but in write buffer mechanism data WRITES to the main memory via a buffer.

Correct choice is (b) HARVARD

Easy explanation: The Harvard architecture have a separate BUS for data and instruction, therefore, it REQUIRES more AREA. It also uses more silicon area for the second SET of tags and the comparators.

The correct choice is (d) no CACHING of WRITING cycle

For explanation: The no caching write cycle does not update the cache but the DATA is written to the cache. If the previous data had cached, that ENTRY is invalid and will not use. This makes the processor fetch data DIRECTLY from the main memory.

Correct choice is (a) MEMORY protection UNIT

Explanation: The memory protection unit allows a tripped memory down memory MANAGEMENT unit in which the memories are partitioned and PROTECTED without any address translation. This can remove the time consumption in the address translation thereby INCREASES the speed.

Correct ANSWER is (a) burst interfaces

Best explanation: The burst interfaces use the burst FILL TECHNIQUE in which the processor will access four words in succession, which fetches the COMPLETE cache line or WRITTEN out to the memory.

Correct choice is (a) descriptor

The explanation is: The address translation from the LOGICAL address to physical address partitions the main MEMORY into different blocks which is CALLED segmentation. Each of these blocks have a descriptor which possesses a descriptor table. So the size of every BLOCK is very IMPORTANT for the descriptor.

Right answer is (C) logical

For EXPLANATION: The SPARC architecture USES logical cache whereas most of the INTERNAL cache designed now, uses physical cache because DATA is not flushed out in this cache.

Correct ANSWER is (a) physical cache

To explain: The physical cache is more efficient and can provide the cache COHERENCY problem solved and MMU delay is kept to a MINIMUM. PowerPC is an EXAMPLE for this ADVANTAGE.

Correct option is (d) paging

For explanation I would say: The paging mechanism SUPPORTS the virtual memory. Paging HELPS in creating virtual ADDRESS SPACE which has a major role in memory management.

The CORRECT choice is (a) global DESCRIPTOR table register

To ELABORATE: The global descriptor table register is a special register which have the linear address and the SIZE of its own GDT. Both the global descriptor table register and local descriptor table register are located in the global descriptor table.

The correct option is (b) SEGMENTATION fault

To explain: DIFFERENT tasks ASSIGN their own address SPACE and whenever a task access memory outside its own address space, a segmentation fault result and which in turn results in the termination of the offending application.

Right option is (C) memory protection unit

Explanation: The memory protection unit have many advantages over the other units. It can REDUCE the chip size, cost and POWER consumption.

The CORRECT answer is (b) descriptor privilege level

For EXPLANATION: The descriptor privilege level is used to restrict access to the segment which helps in PROTECTION mechanism. It ACQUIRES two bit of the descriptor.