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The CORRECT answer is (a) Verilog version 3.0

For explanation I would say: The Verilog VERSIONS 3.0 and 3.1 is called as the SYSTEM Verilog. These INCLUDE several extensions to the Verilog version 2.0.

Correct answer is (B) gate LEVEL MODEL

Explanation: The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate.

Correct option is (a) transaction LEVEL modelling

To elaborate: The transaction level modelling is a TYPE of instruction set level model. This modelling helps in the modelling of components which is used for the communication purpose. It also models the transaction, such as READ and WRITES cycles.

Right choice is (a) SPICE

For explanation: The SPICE is SIMULATION program with integrated circuit emphasis, which is a FREQUENTLY used circuit-level in the early days. It is used to FIND the BEHAVIOR and the INTEGRITY of the circuit.

The correct CHOICE is (B) SystemC 2.0

The explanation: The SystemC includes several MODELS of the TIME. SYSTEM 2.0 is an integer model to define time and this model also supports physical units such as microseconds, nanoseconds, picoseconds etc.

Correct option is (a) SystemC 1.0

For explanation I would say: The SystemC INCLUDES several models of the TIME units. SystemC 1.0 uses floating point numbers which DENOTE time.

The CORRECT option is (d) ALGORITHMIC level

To ELABORATE: The algorithmic level simulates the algorithm which is used within in the embedded SYSTEM.

Right choice is (d) Verilog

For explanation: The Verilog is a hardware DESCRIPTION language which was DEVELOPED for MODELLING hardware and ELECTRONIC devices. This was LATER standardised by IEEE standard 1364.

Right ANSWER is (a) very high speed integrated chip

The EXPLANATION: The VHSIC STANDS for very high speed integrated chip and VHDL was designed in the context of the VHSIC, developed by the department of defence in the US.

The correct ANSWER is (b) strength

The best I can EXPLAIN: The SYSTEMS contain electrical SIGNALS of different strengths and it needs to compute the strength and the logic level resulting from a connection of two or more sources of electrical signals. The strength is the abstraction of the signal impedance.

Correct answer is (a) port map

The EXPLANATION: The port map describes the connection between the entity port and the local COMPONENT. The component is declared by component declaration and the entity ports are MAPPED with the port mapping.

Right option is (c) circuit LEVEL model

Easy explanation: The circuit-level model simulation is USED for the circuit THEORY and its components such as the resistors, inductors, CAPACITORS, voltage sources, CURRENT sources. This simulation also involves the partial differential equations.

The correct answer is (b) wait until

The best explanation: The wait until follows a condition. The condition may be an arithmetic or LOGICAL one and the wait for STATEMENT follows time duration, it might be in MICROSECONDS or NANOSECONDS or any other time unit. Similarly, the wait on statement follows a signal list and the wait statement suspends INDEFINITELY.

Right choice is (d) Moorby and Thomson

Explanation: The Verilog is a hardware description language which was developed by Moorby and Thomson in 1991 and it was standardised as IEEE standard 1364. The Verilog is MODELLED for the ELECTRONICS DEVICES.

Correct answer is (b) register-transfer level

To elaborate: The register-transfer level MODELLING MODELS all the COMPONENTS like the arithmetic and logical unit(ALU), memories, registers, muxes, DECODERS etc and this modelling is always CYCLED truly.

Correct option is (c) SYSTEM level

Explanation: There are a variety of LEVELS for designing the embedded systems and each level has its own language. The system level is one such KIND which has many peculiarities with respect to the other levels. The system model denotes the entire embedded system and includes the mechanical as well as the INFORMATION processing aspects. This also supports the modelling of the partial differential EQUATIONS, which is a key requirement in the modelling.

Right CHOICE is (a) SystemC

To explain: The SystemC is a C++ class which is similar to the hardware description languages like VHDL and Verilog. The EXECUTION and SIMULATION time in the SystemC is ALMOST similar to the VHDL.

Correct ANSWER is (a) WAIT for

To explain I would say: The wait for STATEMENT follows time duration, it might be in MICROSECONDS or NANOSECONDS or any other time unit.

Correct choice is (a) SystemC 2.0

Explanation: The SystemC 2.0 provides the channel PORT and INTERFACE PORTS for the COMMUNICATION PURPOSE.

The CORRECT OPTION is (a) level

The best I can explain: Most of the systems contain electrical signals of different STRENGTHS and levels. The level of the signal is the ABSTRACTION of the signal voltage and the strength is the abstraction of the signal IMPEDANCE.

The correct choice is (d) fine-grained model

The BEST explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the EXACT NUMBER of clock cycles which is required to RUN an application.

The correct choice is (c) coarse-grained model

The explanation: The coarse-grained model is a kind of the instruction set level MODELLING in which only the EFFECT of instruction is SIMULATED and the timing is not considered. The information which is PROVIDED in the MANUAL is sufficient for this type of modelling.

The correct choice is (a) VHDL-AMS

To explain: The VHDL-AMS is the EXTENSION of the VHDL and this includes the ANALOGUE and MIXED behaviour of the SIGNALS.

Right option is (a) VHDL

The best I can EXPLAIN: The Verilog is LESS flexible compared to the VHDL, that is, it allows the hardware entities to be INSTANTIATED in loops which help to build up a structural DESCRIPTION. But Verilog, on the other hand, focuses more on the built-in features.

Right answer is (a) VHDL simulator

Easy explanation: The VHDL simulator is capable of displaying the output signal waveforms which results from the stimuli or TRIGGER applied to the INPUT.

Right choice is (B) VHSIC hardware description language

The best I can explain: VHDL is the VHSIC(very high speed INTEGRATED CIRCUIT) hardware description language which was developed by three COMPANIES, IBM, Intermetrics and Texas Instruments and the first version of the VHDL is established in the year 1984 and later on the VHDL is standardised by the IEEE.

Right ANSWER is (a) SWITCH model

Easiest explanation: The switch model can be used in the simulation of the TRANSISTORS SINCE the transistor is the very BASIC component in a switch. It is capable of reflecting bidirectional transferring of the information.

Correct choice is (d) VHDL

To EXPLAIN I WOULD SAY: The VHDL is the hardware description language which describes the hardware whereas the C, C++ and JAVA are software languages.

The correct answer is (a) Verilog

Best explanation: The Verilog supports the multiple-valued LOGIC with eight DIFFERENT SIGNAL strength but Verilog is LESS flexible compared to the VHDL, that is, it allows the hardware entities to be instantiated in loops which help to build up a STRUCTURAL description.

Correct answer is (c) DESIGN ENTITY

Best EXPLANATION: Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are TWO TYPES of ingredients are used. These are the entity declaration and the architecture declaration.

Correct choice is (a) gate-level MODEL

To explain I would say: The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate. This model is also useful in the power estimation since it PROVIDES accurate INFORMATION about the signal transition probabilities.

Right option is (b) IEEE STANDARD 1364-1995

Best explanation: The IEEE standard 1364-1995 is the FIRST VERSION of the VERILOG and IEEE standard 1394-2001 is the Verilog version 2.0.

Correct CHOICE is (b) Electronic-system level

To EXPLAIN I would say: The ESL is electronic-system level and the SystemC is associated with the ESL and TLM. The SystemC is also applied to the architectural EXPLORATION, performance modelling, SOFTWARE development and so on.

The correct answer is (c) Hayes

The best I can explain: The CSA THEORY is PROPOSED by Hayes and this theory is based on the SYSTEMATIC way of BUILDING up VALUE sets.

The correct OPTION is (b) layout MODEL

For explanation I WOULD say: The layout reflects the ACTUAL circuit model. It includes the geometric information and cannot be simulated directly since it does not provide the information regarding the behavior.

Right choice is (a) VHDL

Easiest explanation: The Verilog and VHDL are HARDWARE description LANGUAGE and these are similar in their CHARACTERISTICS and have a similar number of USERS. The VHDL is more popular in Europe. The Verilog is more popular in the US.

Right choice is (c) System VERILOG

The best explanation: The System Verilog is a superset of the Verilog. But later on, System Verilog and Verilog has merged into a NEW IEEE STANDARD 1800-2009.

Right answer is (d) Verilog

For EXPLANATION: The Verilog offers more FEATURES than the VHDL but VHDL is more FLEXIBLE compared to the Verilog. The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.