Which hardware description language is more flexible?(a) VHDL(b) Verilog(c) C(d) C++This question was addressed to me in an online interview.This intriguing question comes from Verilog and System Verilog in Embedded System topic in division Specification of Embedded Systems

Which hardware description language is more flexible?(a) VHDL(b) Veril

1.	Which hardware description language is more flexible?(a) VHDL(b) Verilog(c) C(d) C++This question was addressed to me in an online interview.This intriguing question comes from Verilog and System Verilog in Embedded System topic in division Specification of Embedded Systems
Answer» Right option is (a) VHDL The best I can EXPLAIN: The Verilog is LESS flexible compared to the VHDL, that is, it allows the hardware entities to be INSTANTIATED in loops which help to build up a structural DESCRIPTION. But Verilog, on the other hand, focuses more on the built-in features.

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