71 + Interview Questions in Interrupts and Exceptions in Embedded Systems Page 1 InterviewSolution

1.	Which exceptions are used in the PowerPC for floating point?(a) synchronous imprecise(b) asynchronous imprecise(c) synchronous precise(d) synchronous impreciseThe question was posed to me at a job interview.The origin of the question is RISC Exceptions in portion Interrupts and Exceptions of Embedded Systems
Answer» Right answer is (a) synchronous IMPRECISE The BEST explanation: The POWERPC can HANDLE the floating point exception by making use of the synchronous imprecise MODE.

Discussion

2.	Which of the exceptions are usually a catastrophic failure?(a) imprecise exception(b) precise exception(c) synchronous exception(d) asynchronous exceptionThe question was asked in an internship interview.This interesting question is from RISC Exceptions topic in portion Interrupts and Exceptions of Embedded Systems
Answer» The correct CHOICE is (a) IMPRECISE exception To EXPLAIN I would say: An imprecise exception is a catastrophic failure in which the processor cannot continue PROCESSING or allow a particular TASK or program to continue.

Discussion

3.	Which bits control the floating point exceptions?(a) EE(b) FE0(c) FE1(d) both FE1 and FE2I got this question by my school teacher while I was bunking the class.Query is from RISC Exceptions-II topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (d) both FE1 and FE2 Easiest EXPLANATION: The FE0 and FE1 CONTROL the FLOATING POINT exceptions.

Discussion

4.	Which of the following are the exceptions associated with the asynchronous imprecise?(a) decrementer interrupt(b) machine check(c) instruction dependent(d) external interruptI had been asked this question by my college professor while I was bunking the class.My doubt stems from RISC Exceptions-II in division Interrupts and Exceptions of Embedded Systems
Answer» Correct ANSWER is (b) MACHINE check To explain I would SAY: The machine check and the system reset are two TYPES of EXCEPTIONS which are associated with the asynchronous imprecise.

Discussion

5.	Which interrupts generate fast interrupt exception?(a) internal interrupt(b) external interrupt(c) software interrupt(d) hardware interruptThis question was posed to me during an interview.The origin of the question is Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (b) external INTERRUPT The EXPLANATION: The external interrupts GENERATES the fast interrupt routine exception in which the external interrupt is synchronised with the processor clock.

Discussion

6.	How is the machine check exception is taken in an asynchronous imprecise?(a) ME bit(b) EE bit(c) FE0(d) FE1I got this question at a job interview.Origin of the question is RISC Exceptions-II topic in portion Interrupts and Exceptions of Embedded Systems
Answer» The correct CHOICE is (a) ME bit Explanation: The MACHINE check exception is taken only if the ME bit of the MSR is set. If it is CLEARED, the PROCESSOR will ENTER into a check stop state.

Discussion

7.	Which of the following uses clock edge to generate an interrupt?(a) edge triggered(b) level-triggered(c) software interrupt(d) nmiI have been asked this question during an online interview.Query is from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems
Answer» Right option is (a) EDGE triggered The explanation is: In the edge-triggered INTERRUPT, the clock edge is used to GENERATE an interrupt. The transition is from a logical low to high or VICE VERSA.

Discussion

8.	What does the RISC processor use to hold the data?(a) flag register(b) accumulator(c) internal register(d) stack registerI got this question in semester exam.Question is taken from The mechanism of Interrupts in section Interrupts and Exceptions of Embedded Systems
Answer»

Discussion

9.	Which part of the software performs tasks in response to the interrupts?(a) background(b) foreground(c) lateral ground(d) both foreground and backgroundI have been asked this question during an interview for a job.The doubt is from Introduction of Interrupts topic in division Interrupts and Exceptions of Embedded Systems
Answer» Right option is (b) FOREGROUND Explanation: In the foreground WORK, the tasks are performed in response to the interrupts but in the BACKGROUND work, the tasks are performed while waiting for an INTERRUPT.

Discussion

10.	Into how many parts does the interrupt can split the software?(a) 2(b) 3(c) 4(d) 5This question was addressed to me in an interview for job.My enquiry is from Introduction of Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» The CORRECT option is (a) 2 To explain: The software interrupt can split into two parts. These are foreground WORK and BACKGROUND work.

Discussion

11.	Which bit controls the external interrupts and the decrementer exceptions?(a) FE1(b) FE0(c) EE(d) METhis question was addressed to me by my school principal while I was bunking the class.I'd like to ask this question from RISC Exceptions-II in chapter Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (c) EE To explain I would say: The EE BIT in the MSR controls the external INTERRUPTS and the decrementer EXCEPTIONS.

Discussion

12.	What is the disadvantage of the fast interrupts?(a) stack frame(b) delay(c) size of routine(d) low speedI had been asked this question in semester exam.The above asked question is from Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» The correct choice is (c) size of routine For explanation: The disadvantages associated with the fast interrupt is the size of routine which can be executed and the resources ALLOCATED. In this technique, it ALLOCATES a COUPLE of ADDRESS registers for the fast interrupt routine.

Discussion

13.	Which of the following allows the splitting of the software?(a) wait statement(b) ready(c) interrupt(d) acknowledgementI have been asked this question in an interview for job.This interesting question is from Introduction of Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» The correct choice is (c) interrupt For explanation I would say: The interrupt can make the SOFTWARE into two main PARTS and these are foreground WORK and BACKGROUND work.

Discussion

14.	Which can activate the ISR?(a) interrupt(b) function(c) procedure(d) structureThis question was addressed to me in exam.Question is from Introduction of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems
Answer» Right ANSWER is (a) interrupt For explanation I would say: When the port RECEIVES the data, it will GENERATE an interrupt which in turn ACTIVATES the ISR.

Discussion

15.	Which of the following does not have a stack frame building?(a) hardware interrupt(b) software interrupt(c) non-maskable interrupt(d) fast interruptI got this question in quiz.This interesting question is from Fast Interrupts in division Interrupts and Exceptions of Embedded Systems
Answer» Correct answer is (d) fast INTERRUPT The best I can EXPLAIN: The fast interrupt does not have stack frame building and it does not POSSESS any such delays. This can be CONSIDERED as the ADVANTAGE of the fast interrupts.

Discussion

16.	How many supervisor registers are associated with the exception mode?(a) 2(b) 3(c) 4(d) 5I had been asked this question by my college director while I was bunking the class.The above asked question is from RISC Exceptions topic in portion Interrupts and Exceptions of Embedded Systems
Answer» The CORRECT choice is (a) 2 The explanation: When the EXCEPTION is recognised, the address of the instruction and the machine STATE register(MSR) are stored in the supervisor REGISTERS in the exception mode. There are two supervisor registers SRR0 and SRR1.

Discussion

17.	How many interrupt levels are supported in the MC68000?(a) 2(b) 3(c) 4(d) 7I have been asked this question in an interview.I'd like to ask this question from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems
Answer» RIGHT choice is (d) 7 To elaborate: The MC68000 has an external stack for holding the data. The MC68000 family supports a SEVEN INTERRUPT level which are encoded into THREE interrupt pins.

Discussion

18.	What does 80×86 use to hold essential data?(a) stack frame(b) register(c) internal register(d) flag registerThe question was posed to me during a job interview.Query is from The mechanism of Interrupts topic in division Interrupts and Exceptions of Embedded Systems
Answer» The correct choice is (a) STACK frame The EXPLANATION is: The MC68000 and 80×86 family use stack frame for HOLDING the DATA whereas RISC processors use special INTERNAL registers.

Discussion

19.	In which interrupt, the trigger is dependent on the logic level?(a) edge triggered(b) level-triggered(c) software interrupt(d) nmiThe question was asked by my college professor while I was bunking the class.I want to ask this question from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems
Answer» The correct CHOICE is (b) LEVEL-triggered For explanation I would say: In the level-triggered interrupt, the trigger is completely dependent on the logic level. The processors may require the level to be in a certain clock width so that the shorter pulses which are shorter than the minimum PULSE width are IGNORED.

Discussion

20.	At which point the processor will start to internally process the interrupt?(a) interrupt pointer(b) instruction pointer(c) instruction boundary(d) interrupt boundaryThe question was asked by my school principal while I was bunking the class.My doubt stems from The mechanism of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems
Answer» CORRECT choice is (c) instruction boundary For explanation: After the recognition of the interrupt, and finds that it is not an error condition with the currently executing interrupt, then the interrupt will not be INTERNALLY executed until the current EXECUTION has completed. This point is known as the instruction boundary. At this point, the processor will start to internally process the interrupt.

Discussion

21.	What does SWI stand for?(a) standard interrupt instruction(b) sequential interrupt instruction(c) software interrupt instruction(d) system interrupt instructionThis question was addressed to me in quiz.Asked question is from Sources of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems
Answer» The CORRECT option is (c) SOFTWARE INTERRUPT instruction The explanation: The instruction set of software interrupts are provided by the SPECIAL instruction set. One such is the SWI which is commonly used in Z80.

Discussion

22.	Which bit controls the machine check exceptions?(a) ME(b) FE0(c) FE1(d) EEI have been asked this question by my college director while I was bunking the class.My question is from RISC Exceptions-II topic in division Interrupts and Exceptions of Embedded Systems
Answer» Correct OPTION is (a) ME To explain I would say: The ME bit in the MSR controls the MACHINE check INTERRUPTS.

Discussion

23.	Which exception can be masked by clearing the EE bit to zero in the MSR?(a) synchronous imprecise(b) synchronous precise(c) asynchronous imprecise(d) asynchronous preciseI have been asked this question in exam.The above asked question is from RISC Exceptions in chapter Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (d) asynchronous precise To explain: The asynchronous precise type exceptions can be masked by CLEARING the EE bits in the MSR. This BIT is automatically cleared to zero in the MSR in order to prevent this interrupt CAUSING an EXCEPTION while other exceptions are being PROCESSED.

Discussion

24.	What happens when an exception is completed?(a) TRAP instruction executes(b) SWI instruction executes(c) RFI instruction executes(d) terminal count increasesThe question was posed to me during an internship interview.I need to ask this question from RISC Exceptions topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» The correct answer is (c) RFI instruction executes For explanation I would say: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the PROCESSOR moves to the supervisor mode and STARTS to execute the handler which is associated with the vector table. The handler EXAMINES the DSISR and FPSCR registers and carries out the required function. When it gets COMPLETED the RFI or return-from-interrupt instruction is executed.

Discussion

25.	Which of the following has more priority?(a) system reset(b) machine check(c) external interrupt(d) decrementer interruptThis question was addressed to me in an interview for job.This is a very interesting question from RISC Exceptions-II in section Interrupts and Exceptions of Embedded Systems
Answer» Right answer is (a) system reset Explanation: The system reset has the first priority then comes the MACHINE reset, next priority moves for the INSTRUCTION DEPENDENT, and the next priority is an external interrupt, and last priority level goes for the decrementer interrupt.

Discussion

26.	What does NMI stand for?(a) non-machine interrupt(b) non-maskable interrupt(c) non-massive interrupt(d) non-memory interruptI have been asked this question in an interview for job.Query is from Sources of Interrupts topic in section Interrupts and Exceptions of Embedded Systems
Answer» Correct answer is (B) non-maskable interrupt Explanation: The NMI STAND for the non-maskable interrupt in which the external interrupts cannot be masked out.

Discussion

27.	Which of the following supplies additional data to the software interrupt?(a) internal interrupt(b) external interrupt(c) software interrupt(d) nmiThe question was posed to me during an internship interview.My enquiry is from Sources of Interrupts in division Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (c) software interrupt Easiest explanation: For using the software interrupt more EFFECTIVELY, the additional data are USED, which specifies the type of the request and data parameters are PASSED to the specific ISR. This additional data are offered by certain REGISTERS.

Discussion

28.	Which of the following are accessible by the ISR in software interrupt mechanism?(a) register(b) interrupt(c) nmi(d) memoryI got this question in an interview.I'd like to ask this question from Sources of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems
Answer» Correct option is (a) register Explanation: The ADDITIONAL DATA are offered by certain registers and these additional data are used to SPECIFY the type of the data PARAMETER and the request with the specific ISR when running in the software interrupt mode.

Discussion

29.	In which of the exceptions does the external event causes the exception?(a) synchronous exception(b) asynchronous exception(c) precise(d) impreciseI got this question during an internship interview.I need to ask this question from RISC Exceptions in division Interrupts and Exceptions of Embedded Systems
Answer» Correct answer is (B) ASYNCHRONOUS exception Easiest EXPLANATION: The asynchronous exception is the one in which an EXTERNAL event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are SYNCHRONISED, that is, it is caused by the instruction flow.

Discussion

30.	Which of the following ensures the recognition of the interrupt?(a) interrupt ready(b) interrupt acknowledge(c) interrupt terminal(d) interrupt startI had been asked this question by my college professor while I was bunking the class.This intriguing question originated from The mechanism of Interrupts in division Interrupts and Exceptions of Embedded Systems
Answer» Correct option is (B) interrupt acknowledge Best EXPLANATION: The interrupt level remains asserted until its interrupt ACKNOWLEDGMENT CYCLE ensures the RECOGNITION of the interrupt.

Discussion

31.	How many exceptions does an MC68000 have?(a) 256(b) 128(c) 90(d) 70This question was addressed to me in an international level competition.The query is from Sources of Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» Right choice is (c) 90 For explanation I would SAY: The MC68000 have 256 table ENTRIES which describe 90 exceptions.

Discussion

32.	Which software interrupt is used in MC68000?(a) Internal interrupt(b) TRAP(c) SWI(d) NMIThis question was addressed to me during a job interview.I need to ask this question from Sources of Interrupts topic in division Interrupts and Exceptions of Embedded Systems
Answer» CORRECT answer is (b) TRAP To EXPLAIN I would say: The MC68000 uses a software INTERRUPT mechanism for accessing interrupts from the peripheral in which the instruction are CREATED using the TRAP mechanism.

Discussion

33.	Which factor depends on the number of times of polling the port while executing the task?(a) data(b) data transfer rate(c) data size(d) number of bitsI had been asked this question in unit test.My enquiry is from Introduction of Interrupts topic in section Interrupts and Exceptions of Embedded Systems
Answer» Correct OPTION is (b) data TRANSFER RATE The explanation: The data transfer rate can determine the number of times the port is POLLED while executing the TASK.

Discussion

34.	Which of the following can improve the quality and the structure of a code?(a) polling(b) subroutine(c) sequential code(d) concurrent codeI got this question in an international level competition.My question is from Introduction of Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» The correct answer is (B) SUBROUTINE For explanation I would say: The subroutine can improve the quality and the structure of the code. By USING the polling METHOD, as the complexity increases the software structure rapidly fall and it will become inefficient. So the subroutine method is adopted.

Discussion

35.	Which processors use fast interrupts?(a) DSP processor(b) RISC processor(c) CISC processor(d) Harvard processorThe question was asked by my college professor while I was bunking the class.I would like to ask this question from Fast Interrupts in section Interrupts and Exceptions of Embedded Systems
Answer» RIGHT choice is (a) DSP processor Easy explanation: The fast interrupts are used in the DSP PROCESSORS or in MICROCONTROLLERS in which a small routine is executed without saving the CONTEXT of the processor.

Discussion

36.	Which of the following does not support PowerPC architecture?(a) synchronous precise(b) asynchronous precise(c) synchronous imprecise(d) asynchronous impreciseI had been asked this question at a job interview.This intriguing question originated from RISC Exceptions in section Interrupts and Exceptions of Embedded Systems
Answer» The correct CHOICE is (C) synchronous imprecise The EXPLANATION: The synchronous imprecise is USUALLY not SUPPORTED on the PowerPC architecture and also in the MPC601, MPC603 etc.

Discussion

37.	Which of the exceptions allows the system reset or memory fault?(a) imprecise exception(b) precise exception(c) synchronous exception(d) asynchronous exceptionThis question was posed to me by my school teacher while I was bunking the class.I want to ask this question from RISC Exceptions in portion Interrupts and Exceptions of Embedded Systems
Answer» Correct choice is (a) IMPRECISE exception Easiest explanation: The SYSTEM RESET or MEMORY fault falls into the category of imprecise exceptions while accessing the vector table.

Discussion

38.	How many interrupt pins are used in MC68000?(a) 2(b) 3(c) 4(d) 5This question was addressed to me during a job interview.My question is from The mechanism of Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» Correct option is (B) 3 To explain I would say: The MC68000 family supports a seven INTERRUPT LEVEL which are encoded into three interrupt pins. These interrupt pins are IP0, IP1, and IP2.

Discussion

39.	Which part of the software is transparent to the interrupt mechanism?(a) background(b) foreground(c) both background and foreground(d) lateral groundI had been asked this question in an online quiz.I want to ask this question from Introduction of Interrupts in section Interrupts and Exceptions of Embedded Systems
Answer» The correct choice is (a) background To elaborate: The interrupt MECHANISM is TRANSPARENT to the background software, that is, the background software is not AWARE of the EXISTENCE of the foreground software.

Discussion

40.	Which of the following can auto increment the register R1?(a) SCI timer(b) interrupt(c) software interrupt(d) non-maskable interruptThis question was posed to me in homework.This is a very interesting question from Fast Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» CORRECT answer is (a) SCI timer For EXPLANATION: The SCI timer is USED to generate the two instruction fast INTERRUPT that can INCREMENT the register R1 which acts as a simple counter.

Discussion

41.	Which of the following is a stack-based processor?(a) MC68000(b) PowerPC(c) ARM(d) DEC AlphaI have been asked this question during an interview.I would like to ask this question from The mechanism of Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» RIGHT choice is (a) MC68000 Easiest explanation: The MC68000, Intel 80×86 and most of the b-bit controllers are based on the stack-based processors whereas POWERPC, DEC alpha, and ARM are RISC families which have a special INTERNAL register for holding the DATA.

Discussion

42.	How a software interrupt is created?(a) instruction set(b) sequential code(c) concurrent code(d) portingThe question was posed to me in a job interview.My question is taken from Sources of Interrupts in division Interrupts and Exceptions of Embedded Systems
Answer» Correct choice is (a) instruction set For explanation I would say: The SOFTWARE INTERRUPTS INCLUDES a set of instructions for handling interrupts. The instruction set allows a currently executing program to change its flow.

Discussion

43.	The time taken to respond to an interrupt is known as(a) interrupt delay(b) interrupt time(c) interrupt latency(d) interrupt functionI had been asked this question in class test.This interesting question is from Introduction of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems
Answer» CORRECT option is (c) interrupt latency For explanation I would SAY: The interrupts are the most important function of the embedded SYSTEM and are responsible for many problems while debugging the system. The time TAKEN to respond to an interrupt is called the interrupt latency.

Discussion

44.	Which of the following can be used as a reset button?(a) NMI(b) internal interrupt(c) external interrupt(d) software interruptThis question was posed to me in class test.This interesting question is from Fast Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» Correct option is (a) NMI For explanation I would say: The non-maskable interrupt is USED to generate an interrupt to TRY and recover control and therefore, the NMI can be used as a RESET BUTTON.

Discussion

45.	Which of the following is connected to a fault detection circuit?(a) internal interrupt(b) external interrupt(c) NMI(d) software interruptThis question was addressed to me in class test.I want to ask this question from Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems
Answer» CORRECT choice is (c) NMI The best I can explain: The non-maskable interrupt is used to GENERATE an interrupt which can be connected to a fault detection CIRCUIT LIKE WATCHDOG timer or parity checker.

Discussion

46.	How many types of exceptions are associated with the asynchronous imprecise?(a) 1(b) 2(c) 3(d) 4I have been asked this question during an internship interview.My enquiry is from RISC Exceptions-II in division Interrupts and Exceptions of Embedded Systems
Answer» RIGHT option is (B) 2 Explanation: Two types of exceptions are associated with the asynchronous imprecise. These are system RESET and MACHINE checks.

Discussion

47.	Which interrupts allows a protected state?(a) internal interrupt(b) external interrupt(c) software interrupt(d) both internal and external interruptsThis question was addressed to me during an internship interview.I'm obligated to ask this question of Sources of Interrupts in section Interrupts and Exceptions of Embedded Systems
Answer» CORRECT answer is (c) software INTERRUPT Easy explanation: The software interrupt can CHANGE the processor into a protected state by changing the PROGRAM flow.

Discussion

48.	Which of the following can be done to ensure that all interrupts are recognised?(a) reset pin(b) external ready pin(c) handshaking(d) acknowledgmentI have been asked this question during an interview.This question is from RISC Exceptions-II topic in division Interrupts and Exceptions of Embedded Systems
Answer» RIGHT ANSWER is (c) handshaking Easiest explanation: The exception handler performs some kind of handshaking to ENSURE that all the interrupts are recognised.

Discussion

49.	Which exception is used in the external interrupts and decrementer-caused exceptions?(a) synchronous precise(b) asynchronous precise(c) synchronous imprecise(d) asynchronous impreciseI got this question in semester exam.This question is from RISC Exceptions topic in chapter Interrupts and Exceptions of Embedded Systems
Answer» The correct CHOICE is (b) asynchronous precise Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can OCCUR at any time WITHIN the instruction flow.

Discussion

50.	What allows the data protection in the software interrupt mechanism?(a) Different mode(b) Same mode(c) SWI(d) TRAPThe question was asked during an interview for a job.Question is taken from Sources of Interrupts in section Interrupts and Exceptions of Embedded Systems
Answer» RIGHT choice is (a) DIFFERENT mode Easy explanation: The switching between user mode and supervisor mode provides PROTECTION for the processor, that is, the different modes in the software interrupt allows the MEMORY and the associated code and data to be protected from each other.

Discussion

Explore topic-wise InterviewSolutions in .

Which bits control the floating point exceptions?(a) EE(b) FE0(c) FE1(d) both FE1 and FE2I got this question by my school teacher while I was bunking the class.Query is from RISC Exceptions-II topic in chapter Interrupts and Exceptions of Embedded Systems

Which interrupts generate fast interrupt exception?(a) internal interrupt(b) external interrupt(c) software interrupt(d) hardware interruptThis question was posed to me during an interview.The origin of the question is Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems

How is the machine check exception is taken in an asynchronous imprecise?(a) ME bit(b) EE bit(c) FE0(d) FE1I got this question at a job interview.Origin of the question is RISC Exceptions-II topic in portion Interrupts and Exceptions of Embedded Systems

Which of the following uses clock edge to generate an interrupt?(a) edge triggered(b) level-triggered(c) software interrupt(d) nmiI have been asked this question during an online interview.Query is from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems

What does the RISC processor use to hold the data?(a) flag register(b) accumulator(c) internal register(d) stack registerI got this question in semester exam.Question is taken from The mechanism of Interrupts in section Interrupts and Exceptions of Embedded Systems

Into how many parts does the interrupt can split the software?(a) 2(b) 3(c) 4(d) 5This question was addressed to me in an interview for job.My enquiry is from Introduction of Interrupts in portion Interrupts and Exceptions of Embedded Systems

Which bit controls the external interrupts and the decrementer exceptions?(a) FE1(b) FE0(c) EE(d) METhis question was addressed to me by my school principal while I was bunking the class.I'd like to ask this question from RISC Exceptions-II in chapter Interrupts and Exceptions of Embedded Systems

What is the disadvantage of the fast interrupts?(a) stack frame(b) delay(c) size of routine(d) low speedI had been asked this question in semester exam.The above asked question is from Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems

Which of the following allows the splitting of the software?(a) wait statement(b) ready(c) interrupt(d) acknowledgementI have been asked this question in an interview for job.This interesting question is from Introduction of Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems

Which can activate the ISR?(a) interrupt(b) function(c) procedure(d) structureThis question was addressed to me in exam.Question is from Introduction of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems

Which of the following does not have a stack frame building?(a) hardware interrupt(b) software interrupt(c) non-maskable interrupt(d) fast interruptI got this question in quiz.This interesting question is from Fast Interrupts in division Interrupts and Exceptions of Embedded Systems

How many supervisor registers are associated with the exception mode?(a) 2(b) 3(c) 4(d) 5I had been asked this question by my college director while I was bunking the class.The above asked question is from RISC Exceptions topic in portion Interrupts and Exceptions of Embedded Systems

How many interrupt levels are supported in the MC68000?(a) 2(b) 3(c) 4(d) 7I have been asked this question in an interview.I'd like to ask this question from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems

What does 80×86 use to hold essential data?(a) stack frame(b) register(c) internal register(d) flag registerThe question was posed to me during a job interview.Query is from The mechanism of Interrupts topic in division Interrupts and Exceptions of Embedded Systems

Which bit controls the machine check exceptions?(a) ME(b) FE0(c) FE1(d) EEI have been asked this question by my college director while I was bunking the class.My question is from RISC Exceptions-II topic in division Interrupts and Exceptions of Embedded Systems

Which of the following has more priority?(a) system reset(b) machine check(c) external interrupt(d) decrementer interruptThis question was addressed to me in an interview for job.This is a very interesting question from RISC Exceptions-II in section Interrupts and Exceptions of Embedded Systems

What does NMI stand for?(a) non-machine interrupt(b) non-maskable interrupt(c) non-massive interrupt(d) non-memory interruptI have been asked this question in an interview for job.Query is from Sources of Interrupts topic in section Interrupts and Exceptions of Embedded Systems

Which of the following are accessible by the ISR in software interrupt mechanism?(a) register(b) interrupt(c) nmi(d) memoryI got this question in an interview.I'd like to ask this question from Sources of Interrupts topic in portion Interrupts and Exceptions of Embedded Systems

How many exceptions does an MC68000 have?(a) 256(b) 128(c) 90(d) 70This question was addressed to me in an international level competition.The query is from Sources of Interrupts in portion Interrupts and Exceptions of Embedded Systems

Which software interrupt is used in MC68000?(a) Internal interrupt(b) TRAP(c) SWI(d) NMIThis question was addressed to me during a job interview.I need to ask this question from Sources of Interrupts topic in division Interrupts and Exceptions of Embedded Systems

Which of the following can improve the quality and the structure of a code?(a) polling(b) subroutine(c) sequential code(d) concurrent codeI got this question in an international level competition.My question is from Introduction of Interrupts in portion Interrupts and Exceptions of Embedded Systems

Which processors use fast interrupts?(a) DSP processor(b) RISC processor(c) CISC processor(d) Harvard processorThe question was asked by my college professor while I was bunking the class.I would like to ask this question from Fast Interrupts in section Interrupts and Exceptions of Embedded Systems

How many interrupt pins are used in MC68000?(a) 2(b) 3(c) 4(d) 5This question was addressed to me during a job interview.My question is from The mechanism of Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems

Which of the following can auto increment the register R1?(a) SCI timer(b) interrupt(c) software interrupt(d) non-maskable interruptThis question was posed to me in homework.This is a very interesting question from Fast Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems

Which of the following is a stack-based processor?(a) MC68000(b) PowerPC(c) ARM(d) DEC AlphaI have been asked this question during an interview.I would like to ask this question from The mechanism of Interrupts in portion Interrupts and Exceptions of Embedded Systems

How a software interrupt is created?(a) instruction set(b) sequential code(c) concurrent code(d) portingThe question was posed to me in a job interview.My question is taken from Sources of Interrupts in division Interrupts and Exceptions of Embedded Systems

Which of the following can be used as a reset button?(a) NMI(b) internal interrupt(c) external interrupt(d) software interruptThis question was posed to me in class test.This interesting question is from Fast Interrupts topic in chapter Interrupts and Exceptions of Embedded Systems

Which of the following is connected to a fault detection circuit?(a) internal interrupt(b) external interrupt(c) NMI(d) software interruptThis question was addressed to me in class test.I want to ask this question from Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems

How many types of exceptions are associated with the asynchronous imprecise?(a) 1(b) 2(c) 3(d) 4I have been asked this question during an internship interview.My enquiry is from RISC Exceptions-II in division Interrupts and Exceptions of Embedded Systems

What allows the data protection in the software interrupt mechanism?(a) Different mode(b) Same mode(c) SWI(d) TRAPThe question was asked during an interview for a job.Question is taken from Sources of Interrupts in section Interrupts and Exceptions of Embedded Systems