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Correct option is (c) MC68300

The best EXPLANATION: The MC68300 combines the processors ALONG with the DMA controllers. The processors which support the MC68300 series are MC68000 or MC68020.

Right choice is (b) RD

To elaborate: RD and WR signals are INDICATING the type of access that the CPU needs to perform, that is, whether it is a read cycle or WRITE cycle.

The correct CHOICE is (d) interrupt signal

Easiest EXPLANATION: The interrupt signal can identify the ERROR OCCURRED in the DMA controller. This makes the processor to reprogram the DMA controller for a different transfer.

The correct CHOICE is (B) EXTERNAL timer

To explain: The baud RATE is SUPPLIED by the counter or an external timer called baud rate generator which generates a clock signal.

Right choice is (c) Phillips

For explanation: The I2C is DEVELOPED by Philips for USE within the television sets.

The correct ANSWER is (c) time

Explanation: The time taken for the data TRANSMISSION within the system depends on the CLOCK FREQUENCY and the number of bits that are transferred.

The correct option is (a) SLAVE select

Easy explanation: The slave select signal SELECTS which slave is to receive DATA from the MASTER.

The correct choice is (a) first byte

The best explanation: The SLAVE selection is performed by using the first byte as an address byte. When the address byte is sent out all the slave devices compares the address by its own VALUE. If there is a MATCH, the ACKNOWLEDGE signal will be sent by the slave.

The correct option is (a) programmable one-shot

Explanation: Mode 1 of the Intel 8253 can provide pulse WIDTH MODULATION for the power CONTROL where the gate is connected to a zero crossing detector or a CLOCK source.

Right answer is (a) SPI

Easiest explanation: The serial peripheral interface ALLOWS the full duplex SYNCHRONOUS communication between the MASTER and the slave devices. MC68HC05 DEVELOPED by MOTOROLA uses SPI for interfacing the peripheral devices.

Right option is (b) switch

Best explanation: The LEDs, ALPHANUMERIC DISPLAYS, seven segment displays are interfaced for the output WHEREAS the switch is an INPUT port.

The correct option is (c) 1D MODEL

Easy explanation: The 1D model of the DMA CONTROLLER USES an ADDRESS location and a counter to define the address sequence which is used during the DMA cycles.

Correct choice is (B) SINGLE address model

For explanation: The single address model is ALSO known as implicit model because the second address is implied and is not DIRECTLY given, that is, the source address is not SUPPLIED.

Right choice is (a) data BUS

The explanation is: The data bus is used for the TRANSMISSION of data from the DMA controller to the destinal. The DMA controller can directly select the peripheral in some cases in which the data TRANSFER is MADE from the peripheral to the memory.

Correct answer is (b) software handshaking

The EXPLANATION is: The Apple MACINTOSH and UNIX USE software handshaking for the data transmission where the characters are sent to control the flow of characters between two systems.

Right OPTION is (d) 6

Best explanation: The 6th pin in DB-25 indicates DSR, that is, DATA SET ready which indicates that each side is POWERED on and is ready to access data.

Correct answer is (a) MR

To ELABORATE: MR is the MASTER reset PIN which helps to reset the DEVICE and restore the internal registers.

Correct option is (a) auto-incrementing COUNTER

For explanation: The peripherals which have a small number of locations can USE auto-increment counter WITHIN the peripheral in which each access selects the NEXT register.

The CORRECT choice is (a) auto-incrementing counter

The explanation: The peripheral having a small number of LOCATIONS can USE auto-incrementing counter for accessing the next register. But this will not be applicable in bigger MEMORY DEVICES.

The correct option is (d) software triggered STROBE

To elaborate: The software triggered strobe can be used as a software-based WATCHDOG TIMER in which the OUTPUT is connected to a non maskable INTERRUPT.

Right CHOICE is (c) LEDs

To elaborate: The KEYBOARDS, switches, and knobs are used as output WHEREAS the LEDs are used as the INPUT port.

Right OPTION is (a) multifunction I/O port

To elaborate: The multifunction I/O port can also be used a chip SELECT for the memory design. The function that the pin performs is SET up internally through the use of a function REGISTER which internally configures how the external pins are CONNECTED internally.

Right answer is (d) DB-25

For EXPLANATION: There are two connectors which are used very commonly. They are DB-25 and DB-9 which has 25 PINS and 9 pins RESPECTIVELY.

The correct answer is (a) polling

Best explanation: The polling can be used ALONG with the counter to DETERMINE the TIMEOUT VALUE.

Correct answer is (b) programmable one-shot

Explanation: Programmable one-shot is also known as mode 1 in the Intel 8253. In mode 1, a SINGLE pulse with a programmable duration is created FIRST and then the pulse LENGTH is loaded into the counter and when the external gate signal is HIGH, the rising edge starts the counter to count down to zero and the counter output signal goes high to start the external pulse. When the counter reaches to zero, the counter output goes LOW and thus the ending of the pulse.

Correct choice is (a) VERIFY transfer mode

For explanation: The verify address transfer mode can GENERATE dummy ADDRESSES which are used for the DRAM refreshing.

Right choice is (d) DMA CPU

Explanation: The DMA CPU is PROGRAMMED with HIGHER level software which is used to transfer the data and for PROCESSING it.

The CORRECT choice is (c) dual address model

The explanation is: The dual address mode supports two addresses and two accesses for transferring data between a PERIPHERAL or memory and another memory LOCATION, which also consumes two bus cycles and a buffer within the DMA CONTROLLER to HOLD data temporarily.

Correct ANSWER is (d) address generator

The explanation: The generic controller have several components associated with it for controlling the OPERATION and one such is the address generator. It CONSISTS of the base address register and an auto-incrementing COUNTER which increment the address after every transfer.

Right CHOICE is (a) clock

The explanation: For SMALL distance communication, the clock signal which ALLOWS a synchronous TRANSMISSION of data is more than enough, and the low voltage signal of TTL or CMOS is sufficient for the operation. But for long distance communication, the clock signal may get skewed and the low voltage can be AFFECTED by the cable capacitance. So for long distance communication RS232 can be used.

The correct option is (C) XIN

Best explanation: The XIN and XOUT PINS are used to connect an EXTERNAL crystal. These pins can also connect an external CLOCK.

Correct answer is (a) XON

To EXPLAIN I would say: The SECOND method of flow CONTROL is called software which is BASED on certain characters called XON and XOFF. XOFF can stop the data TRANSFER and XON can restart the data transfer.

Right CHOICE is (b) DDIS

Easiest explanation: DDIS signal GOES low when the CPU is READING data from the UART and it also CONTROLS the bus ARBITRATION logic.

Correct answer is (a) TIMER

To ELABORATE: The embedded systems have a timing component called timer or counter which HELPS in the timing reference for control sequence, provides system tick for the operating system and also helps in the generation of waveforms for the SERIAL port baud rate generation.

The CORRECT OPTION is (d) mode 4

To explain: The mode 4 is the square WAVE generator. This mode is similar to mode 3 except that the waveform is a square wave.

The CORRECT choice is (d) parallel PORT

The explanation is: The parallel port can transfer multiple bits of data SIMULTANEOUSLY. It provides the input or OUTPUT binary data with a single bit allocated to each pin within the port.

Correct answer is (C) DMA CPU

To EXPLAIN I would say: The DMA CPU has its own address local memory and program so that it will not harm main memory BUS and it is COMPLETELY isolated.

Right choice is (b) external

Explanation: The INTERNAL cycles can be programmed to OCCUPY the PARTIAL or complete fulfillment of the available internal BUS BANDWIDTH while the external cycles provides support to the single transfer modes and burst mode.

The correct choice is (c) verify transfer mode

To explain: In addition to the FOUR main transfer mode, there is a verify transfer mode which is used WITHIN the PC to create dummy addresses which are used for REFRESHING the DRAM.

The correct answer is (b) 5V

Best explanation: The MC1489 is an interface chip which can take a5V and GENERATE internally the other VOLTAGES which are NEEDED to meet the interface specification.

Right option is (a) FLOW CONTROL

Explanation: The flow control can prevent data TRANSMISSION. It can also prevent the computer from SENDING more data than the other can cope with.

Right answer is (B) pre-scalar value

For EXPLANATION I would SAY: The pre-scalar value determines the SLOWEST frequency that can be generated from a given clock input. Actually the bit SIZE are determined by the pre-scalar value and the conuter size.