Which of the following ensures the recognition of the interrupt?(a) interrupt ready(b) interrupt acknowledge(c) interrupt terminal(d) interrupt startI had been asked this question by my college professor while I was bunking the class.This intriguing question originated from The mechanism of Interrupts in division Interrupts and Exceptions of Embedded Systems

Which of the following ensures the recognition of the interrupt?(a) in

1.	Which of the following ensures the recognition of the interrupt?(a) interrupt ready(b) interrupt acknowledge(c) interrupt terminal(d) interrupt startI had been asked this question by my college professor while I was bunking the class.This intriguing question originated from The mechanism of Interrupts in division Interrupts and Exceptions of Embedded Systems
Answer» Correct option is (B) interrupt acknowledge Best EXPLANATION: The interrupt level remains asserted until its interrupt ACKNOWLEDGMENT CYCLE ensures the RECOGNITION of the interrupt.

Discussion

No Comment Found

Related InterviewSolutions

Which exceptions are used in the PowerPC for floating point?(a) synchronous imprecise(b) asynchronous imprecise(c) synchronous precise(d) synchronous impreciseThe question was posed to me at a job interview.The origin of the question is RISC Exceptions in portion Interrupts and Exceptions of Embedded Systems
Which of the exceptions are usually a catastrophic failure?(a) imprecise exception(b) precise exception(c) synchronous exception(d) asynchronous exceptionThe question was asked in an internship interview.This interesting question is from RISC Exceptions topic in portion Interrupts and Exceptions of Embedded Systems
Which bits control the floating point exceptions?(a) EE(b) FE0(c) FE1(d) both FE1 and FE2I got this question by my school teacher while I was bunking the class.Query is from RISC Exceptions-II topic in chapter Interrupts and Exceptions of Embedded Systems
Which of the following are the exceptions associated with the asynchronous imprecise?(a) decrementer interrupt(b) machine check(c) instruction dependent(d) external interruptI had been asked this question by my college professor while I was bunking the class.My doubt stems from RISC Exceptions-II in division Interrupts and Exceptions of Embedded Systems
Which interrupts generate fast interrupt exception?(a) internal interrupt(b) external interrupt(c) software interrupt(d) hardware interruptThis question was posed to me during an interview.The origin of the question is Fast Interrupts in portion Interrupts and Exceptions of Embedded Systems
How is the machine check exception is taken in an asynchronous imprecise?(a) ME bit(b) EE bit(c) FE0(d) FE1I got this question at a job interview.Origin of the question is RISC Exceptions-II topic in portion Interrupts and Exceptions of Embedded Systems
Which of the following uses clock edge to generate an interrupt?(a) edge triggered(b) level-triggered(c) software interrupt(d) nmiI have been asked this question during an online interview.Query is from The mechanism of Interrupts in chapter Interrupts and Exceptions of Embedded Systems
What does the RISC processor use to hold the data?(a) flag register(b) accumulator(c) internal register(d) stack registerI got this question in semester exam.Question is taken from The mechanism of Interrupts in section Interrupts and Exceptions of Embedded Systems
Which part of the software performs tasks in response to the interrupts?(a) background(b) foreground(c) lateral ground(d) both foreground and backgroundI have been asked this question during an interview for a job.The doubt is from Introduction of Interrupts topic in division Interrupts and Exceptions of Embedded Systems
Into how many parts does the interrupt can split the software?(a) 2(b) 3(c) 4(d) 5This question was addressed to me in an interview for job.My enquiry is from Introduction of Interrupts in portion Interrupts and Exceptions of Embedded Systems

Discussion

No Comment Found

Related InterviewSolutions

Reply to Comment