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Suppose You Have A Combinational Circuit Between Two Registers Driven By A Clock. What Will You Do If The Delay Of The Combinational Circuit Is Greater Than Your Clock Signal?

Answer»

Use the CONCEPT of register-retiming.

divide the total combinatorial delay in two SEGMENTS such that INDIVIDUALLY the delay is less the clock period.

this can be done by inserting a flip-flop in the combinational path.

e.g,

clock period --- 5 ns
total cominational delay ---- 7

then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between.

Use the concept of register-retiming.

divide the total combinatorial delay in two segments such that individually the delay is less the clock period.

this can be done by inserting a flip-flop in the combinational path.

e.g,

clock period --- 5 ns
total cominational delay ---- 7

then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between.


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