Saved Bookmarks
This section includes 7 InterviewSolutions, each offering curated multiple-choice questions to sharpen your Current Affairs knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Draw A Transmission Gate-based D-latch? |
|
Answer» The Transmission-Gate's INPUT is CONNECTED to the D_LATCH data input (D), the CONTROL input to the Transmission-Gate is connected to the D_LATCH ENABLE input (EN) and the Transmission-Gate OUTPUT is the D_LATCH output (Q) The Transmission-Gate's input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D_LATCH enable input (EN) and the Transmission-Gate output is the D_LATCH output (Q) |
|
| 2. |
Suppose You Have A Combinational Circuit Between Two Registers Driven By A Clock. What Will You Do If The Delay Of The Combinational Circuit Is Greater Than Your Clock Signal? |
|
Answer» Use the CONCEPT of register-retiming. divide the total combinatorial delay in two SEGMENTS such that INDIVIDUALLY the delay is less the clock period. this can be done by inserting a flip-flop in the combinational path. e.g, clock period --- 5 ns then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between. Use the concept of register-retiming. divide the total combinatorial delay in two segments such that individually the delay is less the clock period. this can be done by inserting a flip-flop in the combinational path. e.g, clock period --- 5 ns then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between. |
|
| 3. |
How Do You Detect A Sequence Of "1101" Arriving Serially From A Signal Line? |
|
Answer» Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero. Ex : if the given sequence to be detected is 111 SOLN: One of the different possible ways to detect a sequence is using a Mealy type FSM. Using the following table the STATE machine can be designed. since the number of bits in the sequence 1101 is 4 we have 4 STATES ------------------------------------------------------ when in state S4 (PS),and input(X) from the sequence is 1,the sequence "1101" has been detected once and (to find the next state select the longest "seq identified by a state" column that MATCHES part of the sequence 1101--ie.,1 or 01 or 101 ....)the NS is S2 since the sequence detected by the state S2 is 1(in 1101- 01 or 101 ,etc are not present in the seq identified by the state column ,) Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero. Ex : if the given sequence to be detected is 111 Soln: One of the different possible ways to detect a sequence is using a Mealy type FSM. Using the following table the State machine can be designed. since the number of bits in the sequence 1101 is 4 we have 4 states ------------------------------------------------------ when in state S4 (PS),and input(X) from the sequence is 1,the sequence "1101" has been detected once and (to find the next state select the longest "seq identified by a state" column that matches part of the sequence 1101--ie.,1 or 01 or 101 ....)the NS is S2 since the sequence detected by the state S2 is 1(in 1101- 01 or 101 ,etc are not present in the seq identified by the state column ,) |
|
| 4. |
Give The Truth Table For A Half Adder. Give A Gate Level Implementation Of The Same? |
|
Answer» TRUTH TABLE FOR HALF ADDER: A B SUM CARRY IMPLEMENTATION:
TRUTH TABLE FOR HALF ADDER: A B SUM CARRY IMPLEMENTATION: |
|
| 5. |
Design A Divide-by-3 Sequential Circuit With 50% Duty Circle? |
|
Answer» Take a SMITHS COUNTER with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively U got divide by 3 FREQ with 50% duty cycle Take a smiths counter with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively u got divide by 3 freq with 50% duty cycle |
|
| 6. |
Give A Circuit To Divide Frequency Of Clock Cycle By Two? |
|
Answer» You can divide the frequency of a CLOCK by just implementing T Flip flop. Give clock as clock input and TIE the T input to logic 1. You can divide the frequency of a clock by just implementing T Flip flop. Give clock as clock input and tie the T input to logic 1. |
|
| 7. |
What Are The Different Adder Circuits You Studied? |
|
Answer» ADDERS are generally of five types: 1) Ripple Carry Adder: The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA). These building blocks HAs and FAs are also the building blocks of all types of adders.The N full adders are cascaded to form n bit RCA. The full adder has three input PINS(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1).Its equations are: Sum=Ai^Bi^Ci Ci+1=Ai.Bi+Bi.Ci+Ai.Ci 2)Carry Lookahead Adder: The Carry Lookahead Adder(CLA) reduces the delay as that in RCA. Let Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci. The expressions for Sum and Ci+1 is then defined completely in terms of input pins rather WAIT for input carry to appear. 3)Carry Select Adder: The carry select adder uses duplicate modules for each combination of input carry(i.e. 1 and 0).The multiplexers then select the APPROPRIATE sum and carry output according to the carry output of the preceding stages. Adders are generally of five types: 1) Ripple Carry Adder: The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA). These building blocks HAs and FAs are also the building blocks of all types of adders.The n full adders are cascaded to form n bit RCA. The full adder has three input pins(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1).Its equations are: Sum=Ai^Bi^Ci Ci+1=Ai.Bi+Bi.Ci+Ai.Ci 2)Carry Lookahead Adder: The Carry Lookahead Adder(CLA) reduces the delay as that in RCA. Let Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci. The expressions for Sum and Ci+1 is then defined completely in terms of input pins rather wait for input carry to appear. 3)Carry Select Adder: The carry select adder uses duplicate modules for each combination of input carry(i.e. 1 and 0).The multiplexers then select the appropriate sum and carry output according to the carry output of the preceding stages. |
|
| 8. |
How To Design A Divide-by-3 Sequential Circuit With 50% Duty Circle? |
|
Answer» TAKE a COUNTER with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively U GOT divide by 3 freq with 50% duty cycle. Take a counter with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively u got divide by 3 freq with 50% duty cycle. |
|
| 9. |
Which Are The Two Ways Of Converting A Two Input Nand Gate To An Inverter? |
|
Answer» Short the TWO inputs of the nand GATE and GIVE the same INPUT to the common wire,the nand gate works as an INVERTER. One way is shorting the two inputs of the NAND gate and passing the input. truth table: A B output The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one. truth table: A B output Short the two inputs of the nand gate and give the same input to the common wire,the nand gate works as an inverter. One way is shorting the two inputs of the NAND gate and passing the input. truth table: A B output The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one. truth table: A B output |
|
| 10. |
How To Detect Sequence Of "1101" Arriving Serially From Signal Line? |
|
Answer» SEQUENCE detector : A sequence detector gives an output of 1 on detecting the GIVEN sequence else the output is zero. Ex : if the given sequence to be detected is 111 and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1. Soln: One of the DIFFERENT POSSIBLE ways to detect a sequence is using a Mealy type FSM. Using the following table the State machine can be designed. Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero. Ex : if the given sequence to be detected is 111 and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1. Soln: One of the different possible ways to detect a sequence is using a Mealy type FSM. Using the following table the State machine can be designed. |
|
| 11. |
Explain What Is Transmission Gate-based D-latch? |
|
Answer» The Transmission-Gate INPUT is connected to the D_LATCH data input (D), the CONTROL input to the Transmission-Gate is connected to the D_LATCH ENABLE input (EN) and the Transmission-Gate output is the D_LATCH output (Q). The Transmission-Gate input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D_LATCH enable input (EN) and the Transmission-Gate output is the D_LATCH output (Q). |
|