Critical defects per unit chip area are ________ for a MOS transistor.(a) High(b) Low(c) Neutral(d) Very HighThe question was asked in class test.This intriguing question comes from MOS Digital Integrated Circuits in division Logic Families of Digital Circuits

Critical defects per unit chip area are ________ for a MOS transistor.

1.	Critical defects per unit chip area are ________ for a MOS transistor.(a) High(b) Low(c) Neutral(d) Very HighThe question was asked in class test.This intriguing question comes from MOS Digital Integrated Circuits in division Logic Families of Digital Circuits
Answer» CORRECT option is (b) LOW To elaborate: CRITICAL defects per unit chip AREA is low for a MOS transistor because it involves fewer STEPS in the fabrication of a MOS transistor. Also, MOSFET has low packaging density.

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