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The correct ANSWER is (b) Variation of a carry-lookahead adder

To ELABORATE: The Manchester carry chain is a variation of the carry-lookahead adder that uses SHARED LOGIC to LOWER the transistor count. However, the carry generating logic depends on the logic to generate the carries in the past.

Right answer is (a) Is cumulative for each stage and limits the speed at which arithmetic OPERATIONS are performed

The explanation is: A FULL adder is a digital circuit with 3 INPUTS and two outputs SUM and CARRY. The carry propagation DELAY in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are performed.

Right OPTION is (b) F

Explanation: Complement means inversion. So, complement of F’ gives back F, as PER the LAW of Involution.

The correct answer is (a) c = xy+xz+yz

Explanation: A full ADDER is a combinational CIRCUIT having 3 INPUTS and 2 outputs, namely SUM and CARRY. The SIMPLIFIED expression of full adder carry is c = xy+xz+yz.

Right option is (d) 8 COMBINATIONAL inputs

To explain: 3 bits FULL ADDER contains 2^3 = 8 combinational inputs.

Correct ANSWER is (d) 512 entries

To EXPLAIN: 2^9 INPUT circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

The correct choice is (b) Binary coded

To explain I would say: Binary-coded decimal (BCD) is a CLASS of binary ENCODINGS of decimal NUMBERS where each decimal digit is REPRESENTED by a FIXED number of bits, usually four or eight. Hexadecimal and Octal are number systems having base 16 and 8 respectively.

Right choice is (c) BCD

The best I can explain: The output sum of TWO decimal digits can be REPRESENTED in BCD(BINARY-coded decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal DIGIT is represented by a fixed number of bits, usually four or eight.

The correct answer is (a) BCD adder

The best explanation: The addition of TWO decimal digits in BCD can be done through BCD adder. Every INPUT inserted, in addition by the user converted into BINARY and then PROCEED for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.

Right option is (c) 4 bits

The explanation: Binary-coded DECIMAL (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC PACKAGES. Each of 4-bit adders is an MSI(MEDIUM SCALE Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.

The CORRECT answer is (a) A single CONDUCTOR

Easiest explanation: A conductor accepts the whole data and arranges it in a serial manner, which is transmitted as binary information. In serial TRANSMISSION, data is transmitted bit by bit while in parallel transmission data is transmitted SIMULTANEOUSLY.

Right answer is (b) Using high-speed clock signals

The best explanation: For any serial data transmission there is REQUIRED of continuously data supply and if the input supply (i.e. high speed clock signals) in a high amount the speed of serial communication can be increased. In serial communication, data is TRANSMITTED BIT by bit. So the use of high speed clock PULSES would MAKE the process faster.

Correct option is (b) MOUNT directly

For explanation I would say: Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBS). An electronic device so made is called a surface-mount device (SMD). In the industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board for components not suited to surface MOUNTING such as large TRANSFORMERS and heat-sinked power semiconductors.

Correct ANSWER is (d) All of the Mentioned

Easy explanation: Transistors are of less CONSUMING POWER, faster, QUIETER, smaller and its implementation is too easy. So, in most applications transistor switches are more preferred. And ALSO, transistors can be current-controlled or voltage-controlled depending on our choice.

Right answer is (d) It is much faster

Explanation: Parallel DATA transmission preferred over SERIAL data transmission for most APPLICATIONS because it is much faster as BITS are transmitted simultaneously, WHEREAS in serial data transmission, bits are transmitted one by one.

Right OPTION is (C) 0.8 MHz

For explanation I would say: By using the formula of frequency, we can find the frequency of clock WAVEFORM. TIME period(t) of the waveform is = 1.25microseconds

F=1/t

Where ‘t’ is the time taken by the clock waveform;

f=(1/1.25)

so, f=0.8 MHz.

The correct choice is (c) Data BUS

To explain: A process consists of 3 types of BUSES: Control Bus, Data Bus and Address Bus. A computer’s data is always in the binary form which is stored in the bus that transmits the data on any CHANNELS. It doesn’t matter that it’s in parallel or serial.

Right answer is (a) 444 NS

The BEST explanation: Because the clock pulse of 4-bit transmits the data of 8-bit WORD in parallel MODE and this transmission is done at 2.25 MHz frequency. We know that: f=1/t and we can find the time required for this transmission by the clock pulse.

Therefore, time = (1/2.25) = 0.4444 US = 444.44 ns ~ 444ns.

Right option is (b) 1

Easy explanation: If minuend = 0, subtrahend = 1 and BORROW INPUT = 1 in a full subtractor then the borrow output will be 1. Because on subtracting 0 and 1, one borrow is TAKEN and it proceeds till the next STEP (i.e 0 – 1 – 1 = 0, borrow = 1).

The correct option is (a) The carry OUTPUT of the lower ORDER stage is CONNECTED to the carry input of the next HIGHER order stage

To explain I would say: When the carry output of the lower order stage is connected to the carry input of the next higher order stage, such types of connection is CALLED ripple carry adder in a 4-bit binary parallel adder.

The CORRECT CHOICE is (c) It is used to STORE the CARRY output of the full adder

Easy EXPLANATION: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be added to the next significant position of the numbers in the registers.

Correct ANSWER is (c) 2

The BEST explanation: There are two shift registers are used in a 4-BIT serial adder, which is used to store the numbers to be added serially. Serial ADDITION takes PLACE bit by bit.

Correct CHOICE is (C) Bit by bit

To EXPLAIN: In serial addition, the addition is carried out bit by bit.

The correct choice is (d) Augend, addend

Explanation: The carry look AHEAD adder is based on the principle of looking at the lower order BITS of the augend and addend if a HIGH order carry is GENERATED. A carry look ahead adder is a type of adder which reduces the propagation delay.

Right answer is (b) If all of the output are independent of the inputs

The EXPLANATION is: If the INPUT is EITHER 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate COMBINATIONS.

The correct answer is (a) 2

The best I can explain: SINCE in the given expression two inputs are complemented. So, we REQUIRE two NOT gate at the input. A NOT gate is a basic gate which ACCEPTS a SINGLE input and produces a single output, which is the inverted version of the input.

Right option is (d) The exclusive-OR OUTPUT is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse

Best explanation: When both the INPUT pulses are high or low X-OR output is low. But when one of the input is high and another is low or vice-versa, output is high. In this PROBLEM for the first 20uS one input is high and another is low. So, OBVIOUSLY output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15) first input is still high and SECOND one is low so output is high.

The correct CHOICE is (b) 1

Best EXPLANATION: The INVERTER can be produced with the help of SINGLE NAND gate, because we can send a single input twice through the same NAND gate TOGETHER, thus producing the inverted version of the input as output. It works as an inverter.

Right choice is (d) To SPEED up the circuit

For explanation: A Carry Look AHEAD (CLA) Adder is a type of adder that REDUCE the propagation delay. A fast Carry Look Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be implemented on any TYPES of chip and have the capability to reduce propagation delay, which HELPS in increasing the speed of 7483 4-bit full-adder.

Correct CHOICE is (d) SIGMA

Easy explanation: The SUMMING OUTPUTS of a half or full-adder are DESIGNATED by “sigma” which is a Greek symbol. This same symbol is used to signify the Minterms in case of an SOP expression.

Correct CHOICE is (d) Both propagation delay and capacitive load

To elaborate: Propagation delay is the measure of time taken by the output to go to the NEXT STATE when the INPUT is altered. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors CAUSES the propagation delay to increase much more quickly than a regular carry lookahead.

Correct option is (c) Generating and propagating carries

To explain: LOOK Ahead Carry Adder is a TYPE of digital circuit which reduces the propagation DELAY. Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most NATURAL to think of generating and propagating in the context of binary addition, the concepts can be USED more generally than this.

Right answer is (c) INVERTING the B inputs

For explanation: A adder is a digital circuit which adds bits along with a carry BIT from a previous stage, thus producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input END. So, for subtraction to be performed, all the BS terminal should be inverted.

Right option is (b) Reduce propagation delay

To explain I would say: A carry-lookahead adder (CLA) is a type of adder USED in digital LOGIC. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It reduces the propagation delay by MAKING the hardware more complex. The RIPPLE carry design is converted in such a way that carry over a group of bits of the adder BECOMES 2-level logic.

Correct ANSWER is (c) A one will be added to the final result

Explanation: For a 4-bit parallel ADDER, if the carry-in is connected to a logical HIGH, one will be added to the final result as a result because carry-in GIVES output as 1.

Right answer is (b) Arithmetic or logic function

For explanation I would say: An ALU PERFORMS BASIC arithmetic and logic operations and STORES it in the accumulator. Examples of arithmetic operations are addition, subtraction, MULTIPLICATION, and division. Examples of logic operations are comparisons of values such as NOT, AND and OR and any LOGICAL operations.

Right option is (b) Half-adder and full-adder

The explanation: There are two TYPES of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-Adder has 3 inputs. Whereas, both have two OUTPUTS SUM and CARRY.

Correct answer is (d) In a parallel full ADDER, the FIRST stage may be a half adder

To EXPLAIN: By using MAXIMUM of TWO half adders we can make a full adder for the first stage of a Parallel Full adder.

Correct choice is (c) The minuend is left in its original form and the subtrahend is CHANGED to its 2’s-complement

To explain: When performing subtraction by addition in the 2’s-complement system, the minuend is left in its original form and the subtrahend is changed to its 2’s-complement. It is then ADDED to the minuend. If the RESULT has carry, then it’s DROPPED and that’s the FINAL answer. Else, if the result has no carry, then the result is again converted to it’s 2’s complement form and that’s the final answer with a ‘negative’ sign.

Correct option is (a) Difference = 0, borrow = 0

Easiest explanation: The BINARY subtraction of 0 – 0 = 0. THUS, it’s difference is 0 as WELL as it’s borrow.

The correct option is (a) Ex-NOR gate

The BEST explanation: EX-OR gate gives 1 if both inputs are DIFFERENT means 0 or 1 and gives 0 if both are same and EX-NOR is OPPOSITE of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR produces output for even number of 1’s or all 0s, while EXOR produces output for ODD number of 1’s.

Right choice is (a) To control the CIRCUIT’s output into the BUS

Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match the output of one of SEVERAL components. By placing a controlled buffer between each component output and the bus, you can control WHETHER that component’s output is fed ONTO the bus or not.

The CORRECT option is (c) It behaves like a NOT GATE

Best EXPLANATION: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is true, the output is the INVERSION of the other. When one input is FALSE, the output is the non-inversion of the other.

Correct option is (C) Both CONTROLLED BUFFER and NOT gate

The explanation is: Controlled inverter is ALSO known as controlled buffer and NOT gate as well. It is used between output and a bus so that ONE can control whether the output is fed to the bus or not.