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The carry propagation delay in 4-bit full-adder circuits ___________(a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed(b) Is normally not a consideration because the delays are usually in the nanosecond range(c) Decreases in direct ratio to the total number of full-adder stages(d) Increases in direct ratio to the total number of full-adder stages but is not a factor in limiting the speed of arithmetic operationsI have been asked this question in exam.I want to ask this question from 4-Bit Parallel Adder/Subtractor topic in section Arithmetic Circuits of Digital Circuits |
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Answer» Right answer is (a) Is cumulative for each stage and limits the speed at which arithmetic OPERATIONS are performed |
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