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The correct choice is (d) 88 ns

To explain: Maximum PROPAGATION delay is the longest delay between an input changing VALUE and the output changing value. HENCE, 22 * n = 22*4 (SINCE there are 4 FFs) = 88ns.

The correct choice is (a) Each FLIP-flop

The best explanation: A ripple counter is SOMETHING that is DERIVED by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be TAKEN into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

Correct OPTION is (B) IC 7490

The BEST I can explain: IC 7493 is a 4-bit binary ripple counter. It is a MOD-16 counter with 2^4 = 16 states.

Right option is (c) 30 kHz

To elaborate: Cascaded COUNTER containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. So, 5*8*10=400. Applied clock frequency = 12 MHz; HENCE, the LOWEST output frequency POSSIBLE is 12MHz/400=30 kHz.

The correct option is (b) 10

The explanation: Decimal counter is also KNOWN as 10 STAGE counter. So, it has 10 STATES. It is also known as Decade Counter counting from 0 to 9.

The CORRECT answer is (b) 3

The explanation is: COUNTERS are of 3 types, namely, (i)asynchronous/synchronous, (II)single and multi-mode & (III)MODULUS counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter and such like.

Right answer is (a) 1.25 kHz

Easy EXPLANATION: Input clock is GIVEN by 20/2 kHz. So, COUNT on the BASIS of 10 kHz clock. And MSB changes on 8th stage; HENCE, f = 10/8 = 1.25 kHz.

Correct choice is (d) All of the Mentioned

The best explanation: By all of the mentioned IDEAS, an asynchronous binary up COUNTER, made from a series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs REFER to FFs being triggered during a clock TRANSITION from LOW to HIGH or HIGH to LOW.

Correct ANSWER is (a) Up count is active-HIGH, the down count is active-LOW

To explain: The designation MEANS that the up count is active-HIGH, the down count is active-LOW. Active-High means that up-count would be TRIGGERED when clock is 1 else when clock is 0, down-count would be triggered, which is referred to as Active-low.

Correct option is (b) 4 Flip-flops

To explain I would say: 2^N-1 < = N < = 2^n

For modulus-10 counter, N = 10. THEREFORE, 2^3 < = 10 < = 2^4. Thus, n = 4, and therefore, we require 4 FFS.

The correct ANSWER is (c) 4

To ELABORATE: An N-bit bit counter requires n NUMBER of FFs. In a 4-bit up-down counter, there are 4 J-K flip-flops required.

Right choice is (d) Can be altered

The BEST I can explain: In up/down ripple counter once the counting BEGINS, we can SIMPLY change the pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

The CORRECT CHOICE is (a) Up-down COUNTER

Easy explanation: Binary counter that counts incrementally and DECREMENT is called UP-DOWN counter/multimode counter. It alternately counts up and down.

Right answer is (b) The normal OUTPUT of the preceding flip-flop

The EXPLANATION is: In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop. UP-counter COUNTS from 0 to a MAXIMUM VALUE.

Correct option is (c) MULTIMODE counter

Easiest EXPLANATION: UP-DOWN counter is also KNOWN as multimode counter because it has CAPABILITY of counting upward as WELL as downwards.

Correct ANSWER is (d) Up counter & down counter

To explain: As the NAME suggests UP-DOWN, it means that it has up-counter and down-counter as well. It alternatively counts up and down.

The correct option is (d) All of the Mentioned

For explanation I would say: A glitch is a transition that occurs before a signal settles to a specific VALUE. A glitch that appears on the decoded output of a RIPPLE counter is OFTEN difficult to see on an oscilloscope because it is a random event and very fast and it occurs less frequently than the normal decoded output.

The CORRECT choice is (c) Stop counting

Explanation: The RIPPLE counter WOULD stop counting because next flip-flop’s input DEPENDS on the output of the PREVIOUS flip-flop.

Correct choice is (C) 5 MHz

The best explanation: Since a counter is constructed using flip-flops, THEREFORE, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 50NS. So, 4 bits or FFs = 50ns * 4 = 200ns. Clock FREQUENCY = 1/200ns = 5 MHz.

Right choice is (a) STROBING

For explanation I would say: A reliable method for eliminating decoder spikes is the technique called strobing. A STROBE signal validates the availability of DATA on CONSECUTIVE parallel lines.

Correct option is (a) It has a cumulative settling time

For explanation: The main drawback of a RIPPLE counter is that it has a cumulative settling time (i.e. ANOTHER bit is TRANSMITTED just after one CONSEQUENTLY).

Correct OPTION is (d) 60 ns

To ELABORATE: SINCE a counter is CONSTRUCTED using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 15ns. So, 4 bits = 15ns * 4 = 60ns.

Right option is (d) 60 ns

The EXPLANATION is: Since a counter is constructed using flip-flops, therefore, the PROPAGATION delay in the counter occurs only due to the flip-flops. Each BIT has propagation delay = 12ns. So, 5 BITS = 12ns * 5 = 60ns.

Correct choice is (a) Each flip-flop

To explain: A RIPPLE counter is something that is derived by other flip-FLOPS. It’s like a series of Flip Flops. The output of one FF BECOMES the input of the NEXT. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in PRODUCING an output when the input is altered.

Right choice is (b) Pulse operation

The explanation: Whatever the input given to the DEVICES are in the FORM of PULSES always. That is why it is known as a FUNDAMENTAL MODE.

The correct option is (c) SYNCHRONOUS COUNTER

Easy explanation: Synchronous counter doesn’t have propagation delay. Propagation delay refers to the amount of time TAKEN in PRODUCING the output when the INPUT is altered.

Correct CHOICE is (d) Points the memory ADDRESS of the current or the NEXT instruction

For explanation I would say: PROGRAM counter in a digital computer points the memory address of the current or the next instruction which is to be executed.

Right choice is (B) It PROVIDES EXACTLY the same information as the state table

For explanation I would SAY: The state DIAGRAM provides exactly the same information as the state table and is obtained directly from the state table.

Right choice is (a) 20%

The explanation: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty cycle is 2/10*100 = 20%. Since the duty cycle is the RATIO of on-time to the total time.

Correct option is (a) 3

The EXPLANATION: The MINIMUM number of flip-flops used in a counter is given by: 2^(N-1)<=N<=2^n.

Thus, for modulus-5 counter: 2^2 <= N <= 2^3, where N = 5 and n = 3.

The correct option is (B) LPM

Explanation: The library of parameterized modules (LPM) counter in the Altera library has CONTROLS that allow it to count up or down, and PERFORM synchronous parallel LOAD and asynchronous CASCADING.

The correct answer is (d) BCD

The best I can explain: BCD MEANS Binary Coded DECIMAL, which means that decimal numbers coded of binary numbers. It displays the decimal EQUIVALENT of CORRESPONDING binary numbers.

Right answer is (c) The SYSTEM CLOCK

The best I can EXPLAIN: All the information is sent from one end to ANOTHER end through the clock pulse which behaves like a carrier. So, for troubleshooting it should be triggered by the same. Since the system clock is internally produced.

The correct choice is (d) Count in a RANDOM order

The explanation is: A sequential CIRCUIT design is used to count in a random manner which is FASTER than the combinational circuit. It is used for STORING data.

Right OPTION is (d) The maximum number of STATES in a counter sequence

Easy explanation: MODULUS is defined as the maximum number of stages/states a counter has. It is INDEPENDENT of the number of states the counter will ACTUALLY traverse.

The correct choice is (a) Apply the active LEVEL to the CLR input and check all of the Q outputs to see if they are all in their reset STATE

To explain: CLR stands for CLEARING or resetting all states of flip-flop. In order to check the CLR function of a counter, apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state.

Correct choice is (c) 101

The best I can explain: Since, in the down counter, the counter CONTENT is decremented by 1 for EVERY NEGATIVE transition. HENCE, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 101.

Correct answer is (a) 3CB0

The best EXPLANATION: You just DIVIDE the NUMBER by 16 at the end and STORE the remainder from bottom to top.

The CORRECT option is (a) 000

The explanation is: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first negative TRANSITION of the CLOCK, the counter content BECOMES 101.

Right answer is (b) LSB flip-flop

For explanation: Since the LSB flip-flop changes its STATE at each negative transition of CLOCK. That is why LSB flip-flop doesn’t have TOGGLE.

The CORRECT OPTION is (d) 8

Easiest explanation: In a n-bit COUNTER, the total NUMBER of states = 2^n.

Therefore, in a 3-bit counter, the total number of states = 2^3 = 8 states.

Correct answer is (a) It counts in upward MANNER

The BEST EXPLANATION: UP COUNTER counts in an upward manner from 0 to (2^n – 1).

The correct choice is (b) It count in downward MANNER

Explanation: DOWN counter COUNTS in a downward manner from (2^n – 1) to 0.

Correct option is (a) Downward from a maximum count

To explain I would say: As the name suggests down COUNTER means COUNTING occurs from a higher value to lower value (i.e. (2^n – 1) to 0).