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Correct choice is (a) D=JQ(p)’+Q(p)K’

Best EXPLANATION: A CHARACTERISTIC equation is needed when a specific GATE requires a specific output in order to SATISFY the truth table. For D flip-flop to JK flip-flop, the characteristics equation is given by D=JQ(p)’+Q(p)K’.

The correct CHOICE is (c) D

Best explanation: For realisation of D FLIP-FLOP from SR flip-flop, S and R are the actual inputs of the flip flop which is connected together via NOT gate and it is called external INPUT as D.

Right answer is (c) J=S, K=R

The best I can EXPLAIN: The K-map simplification for REALISATION of SR flip-flop from JK flip-flop is GIVEN by: J=S, K=R.

The CORRECT CHOICE is (a) 1

For explanation I would say: For JK flip-flop to SR flip-flop, if S=1, R=0 & PRESENT state is 0 then NEXT state will be 1 because next stage is complement of present stage.

The CORRECT CHOICE is (c) S=1, R=0

To explain: If J=1, K=0 & PRESENT state is 0(i.e. Q(n)=0) then next state will be 1 which results EXCITATION INPUTS as S=1 & R=0.

Correct answer is (a) EXTERNAL INPUTS to S and R

The explanation is: If a JK Flip Flop is required, the inputs are GIVEN to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip flop. So, J and K will be given as external inputs to S and R. As SR flip-flop have invalid state and JK flip-flop don’t.

Right choice is (B) S=0, R=X

Easiest explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND GATES which results as S=0 & R=X(i.e. don’t care).

The CORRECT answer is (b) NEXT state decoder

The explanation: To REALISE one flip-flop using another flip-flop ALONG with a combinational circuit, known as NEXT state decoder which acts as like a flip-flop.

The correct option is (B) Synchronous INPUTS

For explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge or level triggering of the clock pulse. Moreover, flip-flops have a clock input WHEREAS LATCHES don’t. HENCE, known as synchronous inputs.

Right answer is (B) The OUTPUT changes STATE only when the clock input is triggered

The EXPLANATION is: The term SYNCHRONOUS means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock.

The correct answer is (C) BISTABLE devices

To explain I WOULD say: Flip-flops are synchronous bistable devices known as bistable multivibrators as they have 2 stable STATES.

Correct ANSWER is (a) 3

Explanation: There are three types of triggering in a flip-flop, VIZ., level triggering, EDGE triggering and PULSE triggering.

The correct OPTION is (c) Inverter

Easy EXPLANATION: S-R TYPE flip-flop can be converted into D type flip-flop if S is CONNECTED to R through an Inverter gate.

The CORRECT answer is (a) T flip-flop

Easiest EXPLANATION: T flip-flop is free from the race AROUND condition because its output depends only on the input; hence there is no any PROBLEM creates as like TOGGLE.

Correct OPTION is (d) J-K type

To ELABORATE: If one wants to design a binary counter, the PREFERRED type of flip-flop is J-K type because it has capability to recover from TOGGLE condition. SR flip-flop is not suitable as it PRODUCES the “Invalid State”.

Right choice is (b) PULSE TRIGGERED flip flop

The explanation is: The term pulse triggered means the data is entered on the RISING edge of the clock pulse, but the output does not reflect the change until the FALLING edge of the clock pulse.

Correct option is (b) Pulser

The best I can EXPLAIN: Pulser behaves LIKE an arithmetic OPERATOR, to PERFORM the operation or determination of corresponding states.

Right option is (c) negative EDGE triggered

Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. WHEREAS the absence of TRIANGLE symbol IMPLIES that the flip-flop is level-triggered.

Right choice is (d) A 10 KHZ square wave

The best I can EXPLAIN: As one flip flop is used so there are two states AVAILABLE. So, 20/2 = 10Hz frequency is available at the output.

The correct option is (d) Level triggered

Easiest EXPLANATION: The HALF circle on the clock input of a J-K flip-flop mean level triggered. WHEREAS the PRESENCE of TRIANGLE symbol implies that the flip-flop is edge-triggered.

Right option is (b) Edge TRIGGERED

The best I can EXPLAIN: The triangle on the clock INPUT of a J-K flip-flop MEAN edge triggered. Whereas the ABSENCE of triangle symbol implies that the flip-flop is level-triggered.

Right answer is (d) J-K, D, T

Best EXPLANATION: Unlike the SR latch, these CIRCUITS have no INVALID states. The SR latch or flip-flop has an invalid or forbidden state where no output could be determined.

The correct answer is (c) 2

Best explanation: The two STABLE states of combinational CIRCUITS are 1 and 0. Whereas, in flip-flops there is an ADDITIONAL state known as Forbidden State.

The CORRECT choice is (c) The flip-flop requires a clock pulse

To explain: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the PAST as WELL as present states. Whereas, in CASE of combinational circuits, they only depend on the present state.

Correct CHOICE is (C) T flip-flop

To EXPLAIN: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

Right option is (d) Q(N+1)=JQ'(n)+K’Q(n)

The best I can explain: A characteristic equation is needed when a specific gate requires a specific output in ORDER to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).

Right option is (d) The next state is independent of present state

For explanation I would SAY: A CHARACTERISTIC equation is needed when a SPECIFIC GATE requires a specific output in ORDER to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is independent of the present state.

Right answer is (c) Due to its CAPABILITY to transfer the DATA into flip-flop

To EXPLAIN: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.

Correct choice is (B) The output will follow the input on the LEADING edge of the clock

Explanation: Edge-triggered flip-flop means the DEVICE will change state during the rising or falling edge of the clock pulse. The MAIN phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.

Correct choice is (C) The Q output follows the D input when EN is HIGH

The BEST explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input. It stores the VALUE on the data LINE.

The CORRECT choice is (B) Q output follows the input D when the enable is HIGH

For explanation I would SAY: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. It stores the value on the data LINE.

Right answer is (d) Q OUTPUT FOLLOWS the input D when the enable is HIGH

The explanation: If CLOCK is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the VALUE on the data LINE.

Correct option is (a) The logic level at the D input is transferred to Q on NGT of CLK

Explanation: By the truth table of D flip FLOP, we can observe that Q always DEPENDS on D. HENCE, for every negative trigger PULSE, the logic at input D is SHIFTED to Output Q.

The correct CHOICE is (a) Has no effect

Easy explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the SET and reset INPUTS of the NAND flip-flop are kept HIGH.