111 + Interview Questions in Flip-Flops in Digital Circuits Page 2 InterviewSolution

51.	The D flip-flop has ______ output/outputs.(a) 2(b) 3(c) 4(d) 1I had been asked this question in a job interview.Origin of the question is D Flip Flop topic in portion Flip-Flops of Digital Circuits
Answer» Right choice is (a) 2 For explanation: The D flip-flop has TWO outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop stands for “data”. It STORES the value on the data line.

Discussion

52.	A D flip-flop can be constructed from an ______ flip-flop.(a) S-R(b) J-K(c) T(d) S-KI had been asked this question in homework.Question is from D Flip Flop in section Flip-Flops of Digital Circuits
Answer» The CORRECT choice is (a) S-R For EXPLANATION I would say: A D flip-flop can be constructed from an S-R flip-flop by inserting an INVERTER between S and R and assigning the SYMBOL D to the S input.

Discussion

53.	The D flip-flop has _______ input.(a) 1(b) 2(c) 3(d) 4This question was addressed to me in final exam.Query is from D Flip Flop in portion Flip-Flops of Digital Circuits
Answer» The CORRECT answer is (a) 1 The EXPLANATION: The D flip-flop has one input. The D of D-flip-flop STANDS for “data”. It stores the value on the data LINE.

Discussion

54.	In D flip-flop, D stands for _____________(a) Distant(b) Data(c) Desired(d) DelayI got this question at a job interview.This question is from D Flip Flop topic in chapter Flip-Flops of Digital Circuits
Answer» The correct option is (b) DATA The best EXPLANATION: The D of D-flip-flop STANDS for “data”. It STORES the value on the data line.

Discussion

55.	How many flip-flops are in the 7475 IC?(a) 2(b) 1(c) 4(d) 8This question was posed to me during an online interview.My question comes from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The correct option is (c) 4 Easy EXPLANATION: There are 4 flip-flops USED in 7475 IC and those are D flip-flops only.

Discussion

56.	Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________(a) 00(b) 11(c) 01(d) 10I have been asked this question in my homework.The origin of the question is Flip Flops in division Flip-Flops of Digital Circuits
Answer» The correct option is (a) 00 The explanation: EVERY O/P repeats after its MOD. Here mod is 4 (because 2 flip-flops are USED. So mod = 2^2 = 4). So after 4 clock PULSES the O/P repeats i.e. 00.

Discussion

57.	Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.(a) 10.24 kHz(b) 5 kHz(c) 30.24 kHz(d) 15 kHzI have been asked this question in homework.This is a very interesting question from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» Correct answer is (b) 5 KHZ For explanation: 12 flip flops = 2^12 = 4096 Input CLOCK FREQUENCY =20.48*10^6 = 20480000 Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

Discussion

58.	Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________(a) 1 kHz(b) 2 kHz(c) 4 kHz(d) 16 kHzThe question was asked during an interview.I would like to ask this question from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» Correct choice is (b) 2 kHz To explain I would say: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- THIRD flip-flop, 4/2=2:- FOURTH flip-flop. SINCE the output FREQUENCY is determined on basis of the 4^th flip-flop.

Discussion

59.	On a J-K flip-flop, when is the flip-flop in a hold condition?(a) J = 0, K = 0(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 1, K = 1This question was addressed to me during an online exam.My question is from Flip Flops in section Flip-Flops of Digital Circuits
Answer» The correct OPTION is (a) J = 0, K = 0 For explanation: At J=0 k=0 output CONTINUES to be in the same STATE. This is the memory storing state.

Discussion

60.	What is the significance of the J and K terminals on the J-K flip-flop?(a) There is no known significance in their designations(b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH(c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit(d) All of the other letters of the alphabet are already in useI got this question by my school principal while I was bunking the class.Enquiry is from Flip Flops in section Flip-Flops of Digital Circuits
Answer» RIGHT CHOICE is (c) The letters were chosen in HONOUR of JACK Kilby, the inventory of the integrated circuit For explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-flops, the invalid STATE problem is resolved, thus leading to the toggling of states.

Discussion

61.	A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________(a) Constantly LOW(b) Constantly HIGH(c) A 20 kHz square wave(d) A 10 kHz square waveThe question was posed to me in my homework.This is a very interesting question from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» Correct CHOICE is (d) A 10 KHZ SQUARE wave To EXPLAIN I would say: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

Discussion

62.	The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________(a) Parity error checking(b) Ones catching(c) Digital discrimination(d) Digital filteringI have been asked this question during an online exam.Query is from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» RIGHT choice is (b) ONES catching For explanation: Ones catching MEANS that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop RESPONDED and LATCHED it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

Discussion

63.	In J-K flip-flop, “no change” condition appears when ___________(a) J = 1, K = 1(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 0, K = 0I have been asked this question in an online quiz.Question is taken from Flip Flops in section Flip-Flops of Digital Circuits
Answer» Correct answer is (d) J = 0, K = 0 To explain: If J = 0, K = 0, the output remains unchanged. This is the memory STORING STATE.

Discussion

64.	A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________(a) Two AND gates(b) Two NAND gates(c) Two NOT gates(d) Two OR gatesThis question was posed to me by my school principal while I was bunking the class.The doubt is from Flip Flops in division Flip-Flops of Digital Circuits
Answer» The CORRECT ANSWER is (a) TWO AND gates Best EXPLANATION: A J-K flip-flop can be OBTAINED from the clocked S-R flip-flop by augmenting two AND gates.

Discussion

65.	How is a J-K flip-flop made to toggle?(a) J = 0, K = 0(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 1, K = 1I have been asked this question during an online exam.Query is from Flip Flops in section Flip-Flops of Digital Circuits
Answer» Right OPTION is (d) J = 1, K = 1 Easy explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs, where 0 BECOMES 1 and 1 becomes 0. That is device is either set or RESET.

Discussion

66.	The characteristic of J-K flip-flop is similar to _____________(a) S-R flip-flop(b) D flip-flop(c) T flip-flop(d) Gated T flip-flopI got this question in final exam.My question is based upon Flip Flops in portion Flip-Flops of Digital Circuits
Answer» Right option is (a) S-R flip-flop Explanation: In an S-R flip-flop, S REFERS to “SET” WHEREAS R refers to “RESET”. The same BEHAVIOUR is SHOWN by J-K flip-flop.

Discussion

67.	If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________(a) SET(b) RESET(c) Clear(d) InvalidThe question was asked during a job interview.I would like to ask this question from Flip Flops in section Flip-Flops of Digital Circuits
Answer» CORRECT answer is (b) RESET Best EXPLANATION: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset. If S=1, R=0, the flip flop is at the SET condition.

Discussion

68.	Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?(a) Gated JK-latch(b) Gated SR-latch(c) Gated T-latch(d) Gated D-latchI have been asked this question during an internship interview.Origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» Correct option is (d) GATED D-latch The best explanation: Since, both inputs of the D flip-flop are connected through an INVERTER. And this CAUSES reduction in the NUMBER of inputs.

Discussion

69.	The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________(a) Edge-detection circuit(b) NOR latch(c) NAND latch(d) Pulse-steering circuitI have been asked this question in semester exam.This intriguing question originated from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» The correct option is (a) Edge-detection circuit To EXPLAIN I WOULD say: The circuit that is primarily RESPONSIBLE for CERTAIN flip-flops to be designated as edge-triggered is the edge-detection circuit.

Discussion

70.	What is the hold condition of a flip-flop?(a) Both S and R inputs activated(b) No active S or R input(c) Only S is active(d) Only R is activeThis question was addressed to me in an online interview.I'd like to ask this question from Flip Flops in portion Flip-Flops of Digital Circuits
Answer» Right answer is (b) No active S or R input For EXPLANATION: The hold condition in a flip-flop is obtained when both of the INPUTS are LOW. It is the No Change State or MEMORY STORAGE state if a flip-flop.

Discussion

71.	On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________(a) The clock pulse is LOW(b) The clock pulse is HIGH(c) The clock pulse transitions from LOW to HIGH(d) The clock pulse transitions from HIGH to LOWThe question was posed to me during an interview for a job.Enquiry is from Flip Flops in portion Flip-Flops of Digital Circuits
Answer» Correct option is (C) The clock PULSE TRANSITIONS from LOW to HIGH Easy explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is NEGATIVE edge triggered when the transition takes place from high to low.

Discussion

72.	The S-R flip flop consist of ____________(a) 4 AND gates(b) Two additional AND gates(c) An additional clock input(d) 3 AND gatesThe question was posed to me in homework.My enquiry is from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» The CORRECT answer is (b) Two ADDITIONAL AND GATES The explanation is: The S-R FLIP flop consists of two additional AND gates at the S and R inputs of S-R LATCH.

Discussion

73.	When is a flip-flop said to be transparent?(a) When the Q output is opposite the input(b) When the Q output follows the input(c) When you can see through the IC packaging(d) When the Q output is complementary of the inputI got this question by my school teacher while I was bunking the class.The origin of the question is Flip Flops in portion Flip-Flops of Digital Circuits
Answer» The correct option is (B) When the Q output follows the input Easiest explanation: Flip-flop have the property of responding immediately to the changes in its INPUTS. This property is called transparency.

Discussion

74.	One example of the use of an S-R flip-flop is as ____________(a) Racer(b) Stable oscillator(c) Binary storage register(d) Transition pulse generatorI have been asked this question in unit test.This intriguing question comes from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer»

Discussion

75.	What is one disadvantage of an S-R flip-flop?(a) It has no Enable input(b) It has a RACE condition(c) It has no clock input(d) Invalid StateThis question was addressed to me during an online exam.My question comes from Flip Flops in portion Flip-Flops of Digital Circuits
Answer» Correct OPTION is (d) INVALID STATE To explain: The main drawback of s-r flip FLOP is invalid OUTPUT when both the inputs are high, which is referred to as Invalid State.

Discussion

76.	How many types of flip-flops are?(a) 2(b) 3(c) 4(d) 5The question was posed to me in unit test.Query is from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» The CORRECT choice is (c) 4 Easiest explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an ADVANCED version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

Discussion

77.	The difference between a flip-flop & latch is ____________(a) Both are same(b) Flip-flop consist of an extra output(c) Latches has one input but flip-flop has two(d) Latch has two inputs but flip-flop has oneThis question was posed to me in an interview.I'm obligated to ask this question of Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» Right CHOICE is (c) Latches has one input but flip-flop has two The explanation is: Flip-flop is a modified version of LATCH. To DETERMINE the changes in states, an ADDITIONAL CONTROL input is provided to the latch.

Discussion

78.	The characteristic equation of S-R latch is ____________(a) Q(n+1) = (S + Q(n))R’(b) Q(n+1) = SR + Q(n)R(c) Q(n+1) = S’R + Q(n)R(d) Q(n+1) = S’R + Q'(n)RThe question was posed to me during an internship interview.The query is from Flip Flops topic in portion Flip-Flops of Digital Circuits
Answer» Right OPTION is (a) Q(n+1) = (S + Q(n))R’ The explanation is: A characteristic equation is NEEDED when a specific gate requires a specific output in order to satisfy the TRUTH table. The characteristic equation of S-R LATCH is Q(n+1) = (S + Q(n))R’.

Discussion

79.	One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________(a) The inputs of NOR latch are 0 but 1 for NAND latch(b) The inputs of NOR latch are 1 but 0 for NAND latch(c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch(d) The output of NOR latch is 1 but 0 for NAND latchThe question was asked in semester exam.The origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The correct answer is (a) The inputs of NOR LATCH are 0 but 1 for NAND latch To ELABORATE: DUE to INVERTED input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.

Discussion

80.	A NAND based S’-R’ latch can be converted into S-R latch by placing ____________(a) A D latch at each of its input(b) An inverter at each of its input(c) It can never be converted(d) Both a D latch and an inverter at its inputThe question was asked during an online interview.I want to ask this question from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» The correct choice is (d) Both a D LATCH and an inverter at its input Explanation: A NAND based S’-R’ latch can be converted into S-R latch by PLACING either a D latch or an inverter at its input as it’s operations will be COMPLEMENTARY.

Discussion

81.	In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________(a) No change(b) Set(c) Reset(d) ForbiddenI have been asked this question by my college director while I was bunking the class.I need to ask this question from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» CORRECT ANSWER is (a) No change The EXPLANATION is: In a NAND BASED S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It remains in its prior state. This state is used for the STORAGE of data.

Discussion

82.	What is an ambiguous condition in a NAND based S’-R’ latch?(a) S’=0, R’=1(b) S’=1, R’=0(c) S’=1, R’=1(d) S’=0, R’=0I had been asked this question during an interview.I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits
Answer» Right choice is (d) S’=0, R’=0 Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden STATE. This state is ALSO known as an Invalid state as the system goes into an UNEXPECTED situation.

Discussion

83.	The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?(a) Because of inverted outputs(b) Because of triggering functionality(c) Because of cross-coupled connection(d) Because of inverted outputs & triggering functionalityI got this question in final exam.My question is from Flip Flops in portion Flip-Flops of Digital Circuits
Answer» The correct answer is (c) Because of cross-coupled connection For EXPLANATION I would say: The cross-coupled CONNECTIONS from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. MOREOVER, they are REFERRED to as asynchronous because they function in the ABSENCE of a clock pulse.

Discussion

84.	The output of latches will remain in set/reset untill ___________(a) The trigger pulse is given to change the state(b) Any pulse given to go into previous state(c) They don’t get any pulse more(d) The pulse is edge-triggeredI got this question at a job interview.This intriguing question originated from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The correct CHOICE is (a) The trigger pulse is GIVEN to change the state The BEST I can EXPLAIN: The output of LATCHES will remain in set/reset untill the trigger pulse is given to change the state.

Discussion

85.	What is a trigger pulse?(a) A pulse that starts a cycle of operation(b) A pulse that reverses the cycle of operation(c) A pulse that prevents a cycle of operation(d) A pulse that enhances a cycle of operationThis question was posed to me in my homework.The doubt is from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The CORRECT choice is (a) A pulse that starts a CYCLE of operation To elaborate: Trigger pulse is defined as a pulse that starts a cycle of operation.

Discussion

86.	In S-R flip-flop, if Q = 0 the output is said to be ___________(a) Set(b) Reset(c) Previous state(d) Current stateThe question was posed to me at a job interview.This intriguing question originated from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The correct choice is (B) Reset Best explanation: In S-R flip-flop, if Q = 0 the OUTPUT is said to be reset and SET for Q = 1.

Discussion

87.	The basic latch consists of ___________(a) Two inverters(b) Two comparators(c) Two amplifiers(d) Two addersThis question was addressed to me in exam.This intriguing question originated from Flip Flops topic in portion Flip-Flops of Digital Circuits
Answer» CORRECT answer is (a) Two inverters The best I can EXPLAIN: The basic latch CONSISTS of two inverters. It is in the sense that if the OUTPUT Q = 0 then the second output Q’ = 1 and VICE versa.

Discussion

88.	The sequential circuit is also called ___________(a) Flip-flop(b) Latch(c) Strobe(d) AdderThe question was asked in an online quiz.My doubt stems from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» The correct ANSWER is (b) Latch The EXPLANATION: The sequential circuit is also called a latch because both are a memory CELL, which are capable of storing one BIT of INFORMATION.

Discussion

89.	How many types of sequential circuits are?(a) 2(b) 3(c) 4(d) 5I had been asked this question during an interview.This interesting question is from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» Correct answer is (a) 2 The best EXPLANATION: There are two type of SEQUENTIAL circuits viz., (i) SYNCHRONOUS or clocked and (ii) ASYNCHRONOUS or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits FUNCTION in the absence of a clock signal.

Discussion

90.	A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?(a) AND or OR gates(b) XOR or XNOR gates(c) NOR or NAND gates(d) AND or NOR gatesThe question was asked during an interview.My question comes from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» The correct answer is (c) NOR or NAND GATES For EXPLANATION I would say: The basic S-R flip-flop can be CONSTRUCTED by cross coupling of NOR or NAND gates. Cross coupling means the OUTPUT of second gate is fed to the input of first gate and vice-versa.

Discussion

91.	The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called ________________(a) Combinational circuits(b) Sequential circuits(c) Latches(d) Flip-flopsI had been asked this question in my homework.My doubt is from Flip Flops in section Flip-Flops of Digital Circuits
Answer» CORRECT answer is (B) Sequential circuits Easiest explanation: In sequential circuits, the output signals are fed BACK to the input SIDE. So, The circuits WHOSE outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.

Discussion

92.	Whose operations are more faster among the following?(a) Combinational circuits(b) Sequential circuits(c) Latches(d) Flip-flopsThis question was posed to me in a national level competition.Origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» RIGHT answer is (a) Combinational circuits To elaborate: Combinational circuits are often faster than sequential circuits. SINCE the combinational circuits do not require memory elements whereas the sequential circuits NEED memory DEVICES to perform their operations in SEQUENCE. Latches and Flip-flops come under sequential circuits.

Discussion

93.	Which of the following is correct for a gated D-type flip-flop?(a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW(b) The output complement follows the input when enabled(c) Only one of the inputs can be HIGH at a time(d) The output toggles if one of the inputs is held HIGHThe question was asked during an interview for a job.The doubt is from Flip Flops topic in section Flip-Flops of Digital Circuits
Answer» The correct answer is (a) The Q output is EITHER SET or RESET as soon as the D input GOES HIGH or LOW For EXPLANATION: In D flip flop, when the clock is high then the output depends on the input otherwise reminds PREVIOUS output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

Discussion

94.	When both inputs of a J-K flip-flop cycle, the output will ___________(a) Be invalid(b) Change(c) Not change(d) ToggleThe question was asked in my homework.This question is from Flip Flops topic in section Flip-Flops of Digital Circuits
Answer» Correct choice is (c) Not change Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle COMPLETE) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 STABLE states: Latch, Reset, SET and TOGGLE.

Discussion

95.	The truth table for an S-R flip-flop has how many VALID entries?(a) 1(b) 2(c) 3(d) 4The question was asked in quiz.My doubt is from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» RIGHT choice is (c) 3 For explanation I would say: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or UNDEFINED State OCCURS at both S and R being at 1.

Discussion

96.	One example of the use of an S-R flip-flop is as ___________(a) Transition pulse generator(b) Racer(c) Switch debouncer(d) Astable oscillatorThe question was asked during an interview.Enquiry is from Flip Flops topic in division Flip-Flops of Digital Circuits
Answer» The correct CHOICE is (C) Switch debouncer The explanation: The SR flip-flop is very effective in removing the EFFECTS of switch bounce, which is the unwanted noise caused during the switching of electronic devices.

Discussion

97.	Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?(a) Low input voltages(b) Synchronous operation(c) Gate impedance(d) Cross couplingI had been asked this question in examination.I would like to ask this question from Flip Flops topic in chapter Flip-Flops of Digital Circuits
Answer» The correct option is (d) Cross coupling The explanation is: LATCH is a type of bistable MULTIVIBRATOR having TWO stable states. Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and DUE to which latches remain in the latched condition.

Discussion

98.	When both inputs of SR latches are low, the latch ___________(a) Q output goes high(b) Q’ output goes high(c) It remains in its previously set or reset state(d) it goes to its next set or reset stateThe question was asked during a job interview.This question is from Latches in section Flip-Flops of Digital Circuits
Answer» Correct choice is (C) It REMAINS in its previously set or RESET state For explanation I would say: When both inputs of SR latches are LOW, the latch remains in it’s present state. There is no CHANGE in output.

Discussion

99.	When both inputs of SR latches are high, the latch goes ___________(a) Unstable(b) Stable(c) Metastable(d) BistableThe question was posed to me in an interview for internship.Asked question is from Latches in chapter Flip-Flops of Digital Circuits
Answer» Correct choice is (c) METASTABLE The explanation is: When both GATES are IDENTICAL and this is “metastable”, and the device will be in an UNDEFINED state for an indefinite period.

Discussion

100.	When a high is applied to the Set line of an SR latch, then ___________(a) Q output goes high(b) Q’ output goes high(c) Q output goes low(d) Both Q and Q’ go highThe question was posed to me in unit test.Origin of the question is Latches topic in division Flip-Flops of Digital Circuits
Answer» RIGHT ANSWER is (a) Q output goes high The explanation is: S INPUT of an SR LATCH is directly connected to the output Q. So when a high is applied Q output goes high and Q’ low.

Discussion

Explore topic-wise InterviewSolutions in .

The D flip-flop has ______ output/outputs.(a) 2(b) 3(c) 4(d) 1I had been asked this question in a job interview.Origin of the question is D Flip Flop topic in portion Flip-Flops of Digital Circuits

A D flip-flop can be constructed from an ______ flip-flop.(a) S-R(b) J-K(c) T(d) S-KI had been asked this question in homework.Question is from D Flip Flop in section Flip-Flops of Digital Circuits

The D flip-flop has _______ input.(a) 1(b) 2(c) 3(d) 4This question was addressed to me in final exam.Query is from D Flip Flop in portion Flip-Flops of Digital Circuits

In D flip-flop, D stands for _____________(a) Distant(b) Data(c) Desired(d) DelayI got this question at a job interview.This question is from D Flip Flop topic in chapter Flip-Flops of Digital Circuits

How many flip-flops are in the 7475 IC?(a) 2(b) 1(c) 4(d) 8This question was posed to me during an online interview.My question comes from Flip Flops in chapter Flip-Flops of Digital Circuits

On a J-K flip-flop, when is the flip-flop in a hold condition?(a) J = 0, K = 0(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 1, K = 1This question was addressed to me during an online exam.My question is from Flip Flops in section Flip-Flops of Digital Circuits

In J-K flip-flop, “no change” condition appears when ___________(a) J = 1, K = 1(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 0, K = 0I have been asked this question in an online quiz.Question is taken from Flip Flops in section Flip-Flops of Digital Circuits

How is a J-K flip-flop made to toggle?(a) J = 0, K = 0(b) J = 1, K = 0(c) J = 0, K = 1(d) J = 1, K = 1I have been asked this question during an online exam.Query is from Flip Flops in section Flip-Flops of Digital Circuits

The characteristic of J-K flip-flop is similar to _____________(a) S-R flip-flop(b) D flip-flop(c) T flip-flop(d) Gated T flip-flopI got this question in final exam.My question is based upon Flip Flops in portion Flip-Flops of Digital Circuits

What is the hold condition of a flip-flop?(a) Both S and R inputs activated(b) No active S or R input(c) Only S is active(d) Only R is activeThis question was addressed to me in an online interview.I'd like to ask this question from Flip Flops in portion Flip-Flops of Digital Circuits

The S-R flip flop consist of ____________(a) 4 AND gates(b) Two additional AND gates(c) An additional clock input(d) 3 AND gatesThe question was posed to me in homework.My enquiry is from Flip Flops topic in chapter Flip-Flops of Digital Circuits

One example of the use of an S-R flip-flop is as ____________(a) Racer(b) Stable oscillator(c) Binary storage register(d) Transition pulse generatorI have been asked this question in unit test.This intriguing question comes from Flip Flops topic in chapter Flip-Flops of Digital Circuits

What is one disadvantage of an S-R flip-flop?(a) It has no Enable input(b) It has a RACE condition(c) It has no clock input(d) Invalid StateThis question was addressed to me during an online exam.My question comes from Flip Flops in portion Flip-Flops of Digital Circuits

How many types of flip-flops are?(a) 2(b) 3(c) 4(d) 5The question was posed to me in unit test.Query is from Flip Flops topic in division Flip-Flops of Digital Circuits

The characteristic equation of S-R latch is ____________(a) Q(n+1) = (S + Q(n))R’(b) Q(n+1) = SR + Q(n)R(c) Q(n+1) = S’R + Q(n)R(d) Q(n+1) = S’R + Q'(n)RThe question was posed to me during an internship interview.The query is from Flip Flops topic in portion Flip-Flops of Digital Circuits

What is an ambiguous condition in a NAND based S’-R’ latch?(a) S’=0, R’=1(b) S’=1, R’=0(c) S’=1, R’=1(d) S’=0, R’=0I had been asked this question during an interview.I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits

In S-R flip-flop, if Q = 0 the output is said to be ___________(a) Set(b) Reset(c) Previous state(d) Current stateThe question was posed to me at a job interview.This intriguing question originated from Flip Flops in chapter Flip-Flops of Digital Circuits

The basic latch consists of ___________(a) Two inverters(b) Two comparators(c) Two amplifiers(d) Two addersThis question was addressed to me in exam.This intriguing question originated from Flip Flops topic in portion Flip-Flops of Digital Circuits

The sequential circuit is also called ___________(a) Flip-flop(b) Latch(c) Strobe(d) AdderThe question was asked in an online quiz.My doubt stems from Flip Flops topic in division Flip-Flops of Digital Circuits

How many types of sequential circuits are?(a) 2(b) 3(c) 4(d) 5I had been asked this question during an interview.This interesting question is from Flip Flops topic in chapter Flip-Flops of Digital Circuits

A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?(a) AND or OR gates(b) XOR or XNOR gates(c) NOR or NAND gates(d) AND or NOR gatesThe question was asked during an interview.My question comes from Flip Flops in chapter Flip-Flops of Digital Circuits

Whose operations are more faster among the following?(a) Combinational circuits(b) Sequential circuits(c) Latches(d) Flip-flopsThis question was posed to me in a national level competition.Origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits

When both inputs of a J-K flip-flop cycle, the output will ___________(a) Be invalid(b) Change(c) Not change(d) ToggleThe question was asked in my homework.This question is from Flip Flops topic in section Flip-Flops of Digital Circuits

The truth table for an S-R flip-flop has how many VALID entries?(a) 1(b) 2(c) 3(d) 4The question was asked in quiz.My doubt is from Flip Flops topic in chapter Flip-Flops of Digital Circuits

One example of the use of an S-R flip-flop is as ___________(a) Transition pulse generator(b) Racer(c) Switch debouncer(d) Astable oscillatorThe question was asked during an interview.Enquiry is from Flip Flops topic in division Flip-Flops of Digital Circuits

When both inputs of SR latches are high, the latch goes ___________(a) Unstable(b) Stable(c) Metastable(d) BistableThe question was posed to me in an interview for internship.Asked question is from Latches in chapter Flip-Flops of Digital Circuits

When a high is applied to the Set line of an SR latch, then ___________(a) Q output goes high(b) Q’ output goes high(c) Q output goes low(d) Both Q and Q’ go highThe question was posed to me in unit test.Origin of the question is Latches topic in division Flip-Flops of Digital Circuits