Which of the following is correct for a gated D-type flip-flop?(a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW(b) The output complement follows the input when enabled(c) Only one of the inputs can be HIGH at a time(d) The output toggles if one of the inputs is held HIGHThe question was asked during an interview for a job.The doubt is from Flip Flops topic in section Flip-Flops of Digital Circuits

Which of the following is correct for a gated D-type flip-flop?(a) The

1.	Which of the following is correct for a gated D-type flip-flop?(a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW(b) The output complement follows the input when enabled(c) Only one of the inputs can be HIGH at a time(d) The output toggles if one of the inputs is held HIGHThe question was asked during an interview for a job.The doubt is from Flip Flops topic in section Flip-Flops of Digital Circuits
Answer» The correct answer is (a) The Q output is EITHER SET or RESET as soon as the D input GOES HIGH or LOW For EXPLANATION: In D flip flop, when the clock is high then the output depends on the input otherwise reminds PREVIOUS output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

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For D flip-flop to JK flip-flop, the characteristics equation is given by ___________(a) D=JQ(p)’+Q(p)K’(b) D=JQ(p)’+KQ(p)’(c) D=JQ(p)+Q(p)K’(d) D=J’Q(p)+Q(p)KI got this question in quiz.This interesting question is from Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
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