What is an ambiguous condition in a NAND based S’-R’ latch?(a) S’=0, R’=1(b) S’=1, R’=0(c) S’=1, R’=1(d) S’=0, R’=0I had been asked this question during an interview.I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits

What is an ambiguous condition in a NAND based S’-R’ latch?(a) S�

1.	What is an ambiguous condition in a NAND based S’-R’ latch?(a) S’=0, R’=1(b) S’=1, R’=0(c) S’=1, R’=1(d) S’=0, R’=0I had been asked this question during an interview.I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits
Answer» Right choice is (d) S’=0, R’=0 Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden STATE. This state is ALSO known as an Invalid state as the system goes into an UNEXPECTED situation.

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For D flip-flop to JK flip-flop, the characteristics equation is given by ___________(a) D=JQ(p)’+Q(p)K’(b) D=JQ(p)’+KQ(p)’(c) D=JQ(p)+Q(p)K’(d) D=J’Q(p)+Q(p)KI got this question in quiz.This interesting question is from Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
For realisation of D flip-flop from SR flip-flop, the external input is given through ___________(a) S(b) R(c) D(d) Both S and RI have been asked this question in an online quiz.The origin of the question is Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be ___________(a) J=1, K=1(b) J=X, K=1(c) J=1, K=X(d) J=0, K=0The question was asked in an interview for job.This intriguing question originated from Realisation of one Flip-flop using other Flip-flops topic in section Flip-Flops of Digital Circuits
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For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________(a) External inputs to S and R(b) Internal inputs to S and R(c) External inputs to combinational circuit(d) Internal inputs to combinational circuitThe question was asked in an online interview.My question comes from Realisation of one Flip-flop using other Flip-flops in division Flip-Flops of Digital Circuits
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What is an ambiguous condition in a NAND based S’-R’ latch?(a) S’=0, R’=1(b) S’=1, R’=0(c) S’=1, R’=1(d) S’=0, R’=0I had been asked this question during an interview.I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits

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