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Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?(a) Gated JK-latch(b) Gated SR-latch(c) Gated T-latch(d) Gated D-latchI have been asked this question during an internship interview.Origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits

Answer»

Correct option is (d) GATED D-latch

The best explanation: Since, both inputs of the D flip-flop are connected through an INVERTER. And this CAUSES reduction in the NUMBER of inputs.



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