The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________(a) Parity error checking(b) Ones catching(c) Digital discrimination(d) Digital filteringI have been asked this question during an online exam.Query is from Flip Flops in chapter Flip-Flops of Digital Circuits

The phenomenon of interpreting unwanted signals on J and K while Cp (c

1.	The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________(a) Parity error checking(b) Ones catching(c) Digital discrimination(d) Digital filteringI have been asked this question during an online exam.Query is from Flip Flops in chapter Flip-Flops of Digital Circuits
Answer» RIGHT choice is (b) ONES catching For explanation: Ones catching MEANS that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop RESPONDED and LATCHED it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

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