In D flip-flop, if clock input is LOW, the D input ___________(a) Has no effect(b) Goes high(c) Goes low(d) Has effectI have been asked this question during an interview.Origin of the question is D Flip Flop in chapter Flip-Flops of Digital Circuits

In D flip-flop, if clock input is LOW, the D input ___________(a) Has

1.	In D flip-flop, if clock input is LOW, the D input ___________(a) Has no effect(b) Goes high(c) Goes low(d) Has effectI have been asked this question during an interview.Origin of the question is D Flip Flop in chapter Flip-Flops of Digital Circuits
Answer» The correct CHOICE is (a) Has no effect Easy explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the SET and reset INPUTS of the NAND flip-flop are kept HIGH.

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For D flip-flop to JK flip-flop, the characteristics equation is given by ___________(a) D=JQ(p)’+Q(p)K’(b) D=JQ(p)’+KQ(p)’(c) D=JQ(p)+Q(p)K’(d) D=J’Q(p)+Q(p)KI got this question in quiz.This interesting question is from Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
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In D flip-flop, if clock input is LOW, the D input ___________(a) Has no effect(b) Goes high(c) Goes low(d) Has effectI have been asked this question during an interview.Origin of the question is D Flip Flop in chapter Flip-Flops of Digital Circuits

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