Which of the following is correct for a gated D flip-flop?(a) The output toggles if one of the inputs is held HIGH(b) Only one of the inputs can be HIGH at a time(c) The output complement follows the input when enabled(d) Q output follows the input D when the enable is HIGHThis question was addressed to me in an interview for job.My doubt stems from D Flip Flop topic in section Flip-Flops of Digital Circuits

Which of the following is correct for a gated D flip-flop?(a) The outp

1.	Which of the following is correct for a gated D flip-flop?(a) The output toggles if one of the inputs is held HIGH(b) Only one of the inputs can be HIGH at a time(c) The output complement follows the input when enabled(d) Q output follows the input D when the enable is HIGHThis question was addressed to me in an interview for job.My doubt stems from D Flip Flop topic in section Flip-Flops of Digital Circuits
Answer» Right answer is (d) Q OUTPUT FOLLOWS the input D when the enable is HIGH The explanation: If CLOCK is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the VALUE on the data LINE.

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For D flip-flop to JK flip-flop, the characteristics equation is given by ___________(a) D=JQ(p)’+Q(p)K’(b) D=JQ(p)’+KQ(p)’(c) D=JQ(p)+Q(p)K’(d) D=J’Q(p)+Q(p)KI got this question in quiz.This interesting question is from Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
For realisation of D flip-flop from SR flip-flop, the external input is given through ___________(a) S(b) R(c) D(d) Both S and RI have been asked this question in an online quiz.The origin of the question is Realisation of one Flip-flop using other Flip-flops topic in portion Flip-Flops of Digital Circuits
For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be ___________(a) J=1, K=1(b) J=X, K=1(c) J=1, K=X(d) J=0, K=0The question was asked in an interview for job.This intriguing question originated from Realisation of one Flip-flop using other Flip-flops topic in section Flip-Flops of Digital Circuits
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For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then excitation input will be ___________(a) S=0, R=1(b) S=X, R=0(c) S=1, R=0(d) S=1, R=1The question was posed to me in an international level competition.This key question is from Realisation of one Flip-flop using other Flip-flops in portion Flip-Flops of Digital Circuits
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