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In ECL the fanout capability is __________(a) High(b) Low(c) Zero(d) Sometimes high and sometimes lowI had been asked this question in my homework.The doubt is from Emitter-Coupled Logic(ECL) topic in portion Logic Families of Digital Circuits

Answer»

The correct option is (a) HIGH

The best I can explain: If the input impedance is high and the output resistance is low; as a RESULT, the transistors change states QUICKLY, GATE delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of inputs that a single gate output can accept.



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