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• Which operation is performed by an interrupt handler?(a) Saving the current state of the system(b) Loading the interrupt handling code and executing it(c) Once done handling, bringing back the system to the original state it was before the interrupt occurred(d) All of the mentionedI got this question in quiz.The origin of the question is Process Structures topic in division Distributed Communication of Operating System
• How does the Hardware trigger an interrupt?(a) Sending signals to CPU through a system bus(b) Executing a special program called interrupt program(c) Executing a special program called system program(d) Executing a special operation called system callI have been asked this question in quiz.The doubt is from Process Structures topic in section Distributed Communication of Operating System
• In the layered approach of Operating Systems __________(a) Bottom Layer(0) is the User interface(b) Highest Layer(N) is the User interface(c) Bottom Layer(N) is the hardware(d) Highest Layer(N) is the hardwareThis question was addressed to me by my college director while I was bunking the class.I would like to ask this question from Process Structures topic in section Distributed Communication of Operating System
• In an interrupt driven input/output __________(a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready(b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available(c) the CPU receives an interrupt when the device is ready for the next byte(d) the CPU runs a user written code and does accordinglyThe question was asked in an online interview.The doubt is from Process Structures topic in division Distributed Communication of Operating System
• In a programmed input/output(PIO) __________(a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready(b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available(c) the CPU receives an interrupt when the device is ready for the next byte(d) the CPU runs a user written code and does accordinglyI got this question during an internship interview.My question is from Process Structures in chapter Distributed Communication of Operating System
• In a memory mapped input/output __________(a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready(b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available(c) the CPU receives an interrupt when the device is ready for the next byte(d) the CPU runs a user written code and does accordinglyI had been asked this question during an interview for a job.My doubt stems from Process Structures in section Distributed Communication of Operating System
• DMA is used for __________(a) High speed devices(disks and communications network)(b) Low speed devices(c) Utilizing CPU cycles(d) All of the mentionedThe question was posed to me in a national level competition.Question is taken from Process Structures topic in section Distributed Communication of Operating System
• What is an interrupt vector?(a) It is an address that is indexed to an interrupt handler(b) It is a unique device number that is indexed by an address(c) It is a unique identity given to an interrupt(d) None of the mentionedThis question was posed to me in an interview.The question is from Process Structures in division Distributed Communication of Operating System
• What is an ISR?(a) Information Service Request(b) Interrupt Service Request(c) Interrupt Service Routine(d) Information Service RoutineThis question was addressed to me during an online exam.The question is from Process Structures topic in chapter Distributed Communication of Operating System
• What is a trap/exception?(a) hardware generated interrupt caused by an error(b) software generated interrupt caused by an error(c) user generated interrupt caused by an error(d) none of the mentionedI have been asked this question in class test.My doubt is from Process Structures in section Distributed Communication of Operating System