260 + Interview Questions in Memory Devices in Digital Circuits Page 1 InterviewSolution

1.	In dynamic memory, CCD stands for __________(a) Charged Count Devices(b) Change Coupled Devices(c) Charge Coupled Devices(d) Charged Compact DiskThe question was asked during an interview.Origin of the question is Introduction of Memory Devices in portion Memory Devices of Digital Circuits
Answer» Correct option is (B) CHANGE Coupled Devices Easy explanation: In dynamic memory, CCD STANDS for CHARGE Coupled Devices.

Discussion

2.	The example of dynamic memory is __________(a) CCD(b) Semiconductor dynamic RAM(c) Both CCD and semiconductor dynamic RAM(d) Floppy-DiskThe question was asked in an online quiz.This interesting question is from Introduction of Memory Devices in division Memory Devices of Digital Circuits
Answer» CORRECT CHOICE is (c) Both CCD and SEMICONDUCTOR dynamic RAM Easy explanation: The examples of dynamic MEMORIES are CCD and semiconductor dynamic RAM because of the contents of both the memories changes with time.

Discussion

3.	A minute magnetic toroid is also called as __________(a) Large memory(b) Small memory(c) Core memory(d) Both small and large memoryI got this question by my school teacher while I was bunking the class.My doubt stems from Introduction of Memory Devices topic in division Memory Devices of Digital Circuits
Answer» Correct answer is (c) Core MEMORY The explanation: A minute magnetic TOROID is also called as core memory which is made up of a SEMICONDUCTOR. A semiconductor is a device WHOSE electrical conductivity lies between that of conductor and insulator.

Discussion

4.	The very first computer memory consisted of __________(a) A small display(b) A large memory storage equipment(c) An automatic keyboard input(d) An automatic mouse inputThis question was posed to me in a national level competition.This intriguing question originated from Introduction of Memory Devices topic in section Memory Devices of Digital Circuits
Answer» Right answer is (b) A large MEMORY storage equipment To explain: The very first COMPUTER memory consisted of a MINUTE MAGNETIC toroid, which required large, bulky circuit boards STORED in large cabinates.

Discussion

5.	The classic multivibrator circuit is known as ____________(a) Metal-coupled multivibrator(b) Plate-coupled multivibrator(c) Parallel-plate coupled multivibrator(d) Alternate-plate coupled multivibratorThe question was asked in an online quiz.I would like to ask this question from Multivibrators topic in section Memory Devices of Digital Circuits
Answer» Right OPTION is (b) Plate-coupled multivibrator Easy explanation: The CLASSIC multivibrator CIRCUIT (also CALLED a plate-coupled multivibrator) is first described by Henri Abraham and Eugene Bloch.

Discussion

6.	Monostable multivibrator can also be termed as ____________(a) Full astable multivibrator(b) Half astable multivibrator(c) Half bistable multivibrator(d) Full bistable multivibratorThis question was addressed to me in class test.My question is based upon Multivibrators in division Memory Devices of Digital Circuits
Answer»

Discussion

7.	In an astable multivibrator, the amplifying elements are ____________(a) FET(b) JFET(c) OP-AMP(d) All of the MentionedThis question was posed to me during an interview.I want to ask this question from Multivibrators in chapter Memory Devices of Digital Circuits
Answer» The correct OPTION is (d) All of the Mentioned For EXPLANATION I would say: Astable multivibrators are made with FET, JFET, OP-AMP or other types of amplifier. Astable circuit continually SWITCHES from one state to the other. It KEEPS oscillating between unstable states.

Discussion

8.	Astable circuit acts as a/an ____________(a) Amplifier(b) Oscillator(c) Relaxation oscillator(d) MultiplexerI got this question during an online interview.I'd like to ask this question from Multivibrators topic in division Memory Devices of Digital Circuits
Answer» RIGHT option is (c) Relaxation oscillator The explanation is: Astable circuit continually switches from ONE state to the other. It KEEPS OSCILLATING between unstable states. Hence, it FUNCTIONS as a relaxation oscillator.

Discussion

9.	Bistable circuit is also known as ____________(a) Latch(b) Gate(c) Flip-flop(d) Bidirectional circuitThis question was addressed to me in unit test.My question is taken from Multivibrators in division Memory Devices of Digital Circuits
Answer» The correct option is (C) Flip-flop The best I can EXPLAIN: BISTABLE multivibrator CIRCUIT has the capability to store 1-bit of information. So, it is ALSO known as flip-flop. Like Flip-flop, Bistable circuit also has 2 states.

Discussion

10.	Bistable multivibrator is ________ in any state.(a) Stable(b) Unstable(c) Saturated(d) IndependentI got this question in an interview.I want to ask this question from Multivibrators topic in chapter Memory Devices of Digital Circuits
Answer» CORRECT option is (a) Stable The BEST EXPLANATION: BISTABLE MULTIVIBRATOR is a type of multivibrator having two stable states. The circuit is stable in either state. It can be flipped from one state to the other by an external trigger pulse.

Discussion

11.	Monostable multivibrator is/has ________ state.(a) Stable(b) Unstable(c) One stable and another unstable(d) IndependentThe question was posed to me in an interview for job.Asked question is from Multivibrators topic in division Memory Devices of Digital Circuits
Answer»

Discussion

12.	Astable multivibrator is ________ in any state.(a) Stable(b) Unstable(c) Saturated(d) Both Stable & SaturatedI have been asked this question in examination.My question is from Multivibrators topic in division Memory Devices of Digital Circuits
Answer»

Discussion

13.	How many types of multivibrators are?(a) 2(b) 4(c) 5(d) 3I had been asked this question in my homework.My question comes from Multivibrators in portion Memory Devices of Digital Circuits
Answer» Correct ANSWER is (d) 3 For explanation I WOULD say: There are three types of multivibrator circuits DEPENDING on the circuit operation: (i) Astable, (ii) Bistable, and (III) Monostable. Astable multivibrator is internally triggered, whereas the other TWO types are externally triggered.

Discussion

14.	Multivibrators are characterized by ____________(a) Registers(b) Capacitors(c) Transistors(d) All of the MentionedI have been asked this question during an interview.This intriguing question comes from Multivibrators in section Memory Devices of Digital Circuits
Answer» Right option is (d) All of the Mentioned Easiest explanation: A MULTIVIBRATOR is an electronic circuit USED to implement a variety of simple two-state systems and two state systems are an oscillator, TIMER, flip-flop. It produces an output when triggered. MULTIVIBRATORS are characterized by amplifying DEVICES (transistors) and cross coupled devices (registers, capacitors).

Discussion

15.	A multivibrator is an electronic circuit used to implement ____________(a) Oscillator(b) Timer(c) Flip-flop(d) All of the MentionedI have been asked this question in an international level competition.Question is from Multivibrators in chapter Memory Devices of Digital Circuits
Answer» Correct ANSWER is (d) All of the Mentioned Explanation: A multivibrator is an electronic CIRCUIT USED to implement a variety of SIMPLE two-state systems and two state systems are an oscillator, timer, flip-flop. It produces an output when triggered.

Discussion

16.	A major block which is not a part of an HDL frequency counter _____________(a) Timing and control unit(b) Decoder/display(c) Display register(d) Bit shifterThis question was posed to me in an international level competition.My question comes from Introduction to Hardware Description Language in section Memory Devices of Digital Circuits
Answer» RIGHT choice is (d) BIT SHIFTER Explanation: Bit shifter is part of a REGISTER in which bit shifting TAKES place bit-by-bit either left or right.

Discussion

17.	A stepper motor HDL application must include _____________(a) Sequencers and multiplexers(b) Types and bits(c) Counters and decoders(d) Variables and processesThe question was posed to me at a job interview.My doubt is from Introduction to Hardware Description Language topic in portion Memory Devices of Digital Circuits
Answer» The correct OPTION is (c) Counters and decoders The best explanation: A stepper motor (ALSO referred to as STEP or stepping motor) is an electromechanical device achieving mechanical movements through the conversion of ELECTRICAL pulses. A stepper motor HDL application must include counters and decoders for POSITION control. It is tested on the simulator.

Discussion

18.	In the keypad application, the preset state of the ring counter define _____________(a) The NANDing of the columns(b) The NANDing of the rows(c) The proper output of the column encoder(d) The proper output of the row encoderThis question was addressed to me in an interview for internship.Asked question is from Introduction to Hardware Description Language topic in chapter Memory Devices of Digital Circuits
Answer» Correct answer is (d) The proper OUTPUT of the row encoder The best I can explain: When a key is pressed the ring COUNTER in the HDL SCANS the information provided by the user and COUNTS to find the row. The preset state of the ring counter define the proper output of the row encoder.

Discussion

19.	A step which should be followed in project management is known as _____________(a) Overall definition(b) System documentation(c) Synthesis and testing(d) System integrationThis question was addressed to me in homework.My enquiry is from Introduction to Hardware Description Language in portion Memory Devices of Digital Circuits
Answer» Right option is (b) System documentation To elaborate: System documentation is the second STEP of PROJECT MANAGEMENT in which a result of the system is noted simultaneously.

Discussion

20.	When a key is pressed, what does the ring counter in the HDL keypad application do?(a) Count to find the row(b) Freeze(c) Count to find the column(d) Start the D flip-flopI got this question in examination.My question is based upon Introduction to Hardware Description Language in chapter Memory Devices of Digital Circuits
Answer»

Discussion

21.	What does the data signal do in the keypad application?(a) The row and column encoded data(b) The ring encoded data(c) The freeze locator data(d) The ring counter dataI got this question in an international level competition.The above asked question is from Introduction to Hardware Description Language in division Memory Devices of Digital Circuits
Answer» The correct option is (a) The row and COLUMN ENCODED data Best explanation: The data SIGNAL ARRANGES the information with the help of data FLOW in row and column manner. It encodes the data to be sent.

Discussion

22.	In a digital clock application, the basic frequency must be divided down as _____________(a) 1 Hz(b) 60 Hz(c) 100 Hz(d) 1000 HzI had been asked this question in exam.This intriguing question originated from Introduction to Hardware Description Language in portion Memory Devices of Digital Circuits
Answer» Right ANSWER is (a) 1 Hz Easy EXPLANATION: MINIMUM count is 1 sec and TIME = 1/freq. So, t = 1/1 = 1HZ.

Discussion

23.	In an HDL application of a stepper motor, what is done next after an up/down counter is built?(a) Build the sequencer(b) Test it on a simulator(c) Test the decoder(d) Design an intermediate integer variableI had been asked this question in examination.Origin of the question is Introduction to Hardware Description Language in section Memory Devices of Digital Circuits
Answer» CORRECT CHOICE is (b) Test it on a simulator For explanation I would say: Simulator is a software which is used in the TESTING of the STEPPER motor using up/down COUNTER.

Discussion

24.	The output frequency related to the sampling interval of a frequency counter as _____________(a) Directly with the sampling interval(b) Inversely with the sampling interval(c) More precision with longer sampling interval(d) Less precision with longer sampling intervalI have been asked this question in exam.The query is from Introduction to Hardware Description Language in division Memory Devices of Digital Circuits
Answer» The correct OPTION is (C) More precision with longer SAMPLING interval The best explanation: Sampling interval means a particular frequency range in which the device operates correctly. Thus, more precision is PRODUCED with longer sampling interval.

Discussion

25.	At high frequencies when the sampling interval is too long in a frequency counter _____________(a) The counter works fine(b) The counter undercounts the frequency(c) The measurement is less precise(d) The counter overflowsThis question was posed to me during an interview.My question comes from Introduction to Hardware Description Language in section Memory Devices of Digital Circuits
Answer» Correct option is (d) The counter overflows Explanation: LET the sampling time be 1 sec. This means the counter will count the number of PULSES from the unknown signal for 1sec duration and would display it after 1 sec. THUS if the signal is of 800 Hz, at the end of 1 sec, counter would have counted up to 800. Thus, in case of high frequencies and high sampling time, counter might count BEYOND its limit and overflows.

Discussion

26.	The use of VHDL can be done in _____ ways.(a) 2(b) 3(c) 4(d) 5The question was posed to me in class test.Question is taken from Introduction to Hardware Description Language topic in section Memory Devices of Digital Circuits
Answer» The CORRECT answer is (B) 3 The explanation: The VHDL has THREE coding styles are: (i) data flow, (ii) STRUCTURAL, (iii) BEHAVIOURAL.

Discussion

27.	VHDL is being used for _____________(a) Documentation(b) Verification(c) Synthesis oflarge digital design(d) All of the MentionedThe question was asked in an interview for job.The question is from Introduction to Hardware Description Language topic in portion Memory Devices of Digital Circuits
Answer» Correct option is (d) All of the Mentioned To explain I would say: The full form of VHDL is Verilog Hardware Description LANGUAGE. The acronym of VHDL itself captures the entire THEME of the language and it describes the hardware in the same manner as does the schematic. So, it is USED as documentation, verification and synthesis of large digital DESIGNS.

Discussion

28.	VHSIC stands for _____________(a) Very High Speed Integrated Circuits(b) Very Higher Speed Integration Circuits(c) Variable High Speed Integrated Circuits(d) Variable Higher Speed Integration CircuitsI got this question at a job interview.Asked question is from Introduction to Hardware Description Language in section Memory Devices of Digital Circuits
Answer» Correct OPTION is (a) Very High Speed INTEGRATED Circuits The explanation: VHSIC stands for Very High Speed Integrated Circuits.

Discussion

29.	The full form of VHDL is _____________(a) Very High Descriptive Language(b) Verilog Hardware Description Language(c) Variable Definition Language(d) None of the MentionedI have been asked this question by my college director while I was bunking the class.I would like to ask this question from Introduction to Hardware Description Language topic in section Memory Devices of Digital Circuits
Answer» RIGHT option is (b) VERILOG Hardware Description LANGUAGE The best explanation: The full form of VHDL is Verilog Hardware Description Language.

Discussion

30.	The full form of HDL is _________________(a) Higher Descriptive Language(b) Higher Definition Language(c) Hardware Description Language(d) High Descriptive LanguageI had been asked this question in homework.This interesting question is from Introduction to Hardware Description Language topic in section Memory Devices of Digital Circuits
Answer» Right option is (c) HARDWARE DESCRIPTION LANGUAGE The BEST I can explain: The full form of HDL is Hardware Description Language.

Discussion

31.	Applications of PLAs are _____________(a) Registered PALs(b) Configurable PALs(c) PAL programming(d) All of the MentionedI got this question during an interview.The above asked question is from Programmable Array Logic in chapter Memory Devices of Digital Circuits
Answer» The CORRECT answer is (d) All of the Mentioned The BEST I can EXPLAIN: Applications of PLAs are Registered PALs, Configurable PALs, and PAL programming and these are PERFORMED by using an extra flip-flop with PAL.

Discussion

32.	In FPGA, vertical and horizontal directions are separated by ____________(a) A line(b) A channel(c) A strobe(d) A flip-flopThis question was addressed to me during an interview for a job.Origin of the question is Programmable Array Logic in section Memory Devices of Digital Circuits
Answer» Right answer is (b) A channel The explanation: The FPGA REFERS to Field Programmable Gate Array. Field-Programmable Gate Arrays (FPGAs) are reprogrammable silicon chips. Vertical and horizontal DIRECTIONS is SEPARATED by a channel in an FPGA which determines the LOCATION of the OUTPUT.

Discussion

33.	The full form of VLSI is ____________(a) Very Long Single Integration(b) Very Least Scale Integration(c) Very Large Scale Integration(d) Very Long Scale IntegrationThis question was posed to me during an interview for a job.My question comes from Programmable Array Logic topic in section Memory Devices of Digital Circuits
Answer» RIGHT choice is (c) Very Large Scale Integration Easiest EXPLANATION: The full FORM of VLSI is Very Large Scale Integration in which FPGA is IMPLEMENTED.

Discussion

34.	The FPGA refers to ____________(a) First programmable Gate Array(b) Field Programmable Gate Array(c) First Program Gate Array(d) Field Program Gate ArrayThe question was asked in an international level competition.The above asked question is from Programmable Array Logic in portion Memory Devices of Digital Circuits
Answer» RIGHT OPTION is (b) Field Programmable Gate Array To elaborate: The FPGA refers to Field Programmable Gate Array. Field-Programmable Gate Arrays (FPGAs) are reprogrammable silicon chips. In contrast to processors that you FIND in your PC, PROGRAMMING an FPGA rewires the chip itself to implement your functionality rather than run a software APPLICATION. Thus, FPGAs are PLD devices.

Discussion

35.	If a PAL has been programmed once ____________(a) Its logic capacity is lost(b) Its outputs are only active HIGH(c) Its outputs are only active LOW(d) It cannot be reprogrammedI had been asked this question in my homework.This intriguing question comes from Programmable Array Logic topic in portion Memory Devices of Digital Circuits
Answer» Right answer is (d) It cannot be REPROGRAMMED Explanation: PAL only has a PROGRAMMABLE AND plane and a fixed OR plane. SINCE, PAL is dynamic in nature. So, it can’t be reprogrammed.

Discussion

36.	The difference between a PAL & a PLA is ____________(a) PALs and PLAs are the same thing(b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane(c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane(d) The PAL has more possible product terms than the PLAI have been asked this question by my college director while I was bunking the class.I would like to ask this question from Programmable Array Logic in section Memory Devices of Digital Circuits
Answer» Right OPTION is (b) The PLA has a PROGRAMMABLE OR plane and a programmable AND plane, while the PAL only has a programmable AND plane Best explanation: The main DIFFERENCE between a PAL & PLA is that PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane and a fixed OR plane.

Discussion

37.	Which type of device FPGA are?(a) SLD(b) SROM(c) EPROM(d) PLDThe question was asked in an internship interview.I'm obligated to ask this question of Programmable Array Logic in division Memory Devices of Digital Circuits
Answer» Correct option is (d) PLD Explanation: Field-Programmable Gate ARRAYS (FPGAs) are reprogrammable silicon CHIPS. In contrast to processors that you find in your PC, programming an FPGA rewires the chip itself to IMPLEMENT your functionality rather than RUN a software application. Thus, FPGAs are PLD devices.

Discussion

38.	For programmable logic functions, which type of PLD should be used?(a) PLA(b) PAL(c) CPLD(d) SLDThis question was posed to me in examination.The origin of the question is Programmable Array Logic in division Memory Devices of Digital Circuits
Answer» RIGHT OPTION is (b) PAL To EXPLAIN I would SAY: Since PAL consists of programmable AND gates and fixed OR gates and also circuitry WORKING is less.

Discussion

39.	The complex programmable logic device contains several PLD blocks and __________(a) A language compiler(b) AND/OR arrays(c) Global interconnection matrix(d) Field-programmable switchesThis question was addressed to me in quiz.Asked question is from Programmable Array Logic in portion Memory Devices of Digital Circuits
Answer» Right answer is (c) Global interconnection matrix Easiest explanation: The COMPLEX PROGRAMMABLE logic device contains several PLD blocks and a global interconnection matrix by which it communicates through several devices. It is ALSO known as Field-Programmable GATE Arrays (FPGAs).

Discussion

40.	PLA is used to implement ____________(a) A complex sequential circuit(b) A simple sequential circuit(c) A complex combinational circuit(d) A simple combinational circuitThis question was posed to me during an interview.My enquiry is from Programmable Array Logic topic in division Memory Devices of Digital Circuits
Answer» The correct OPTION is (c) A COMPLEX combinational circuit Best explanation: Since, PLA is a COMBINATION of programmable AND and OR GATES. So, it is used to IMPLEMENT complex combinational circuit.

Discussion

41.	A PLA is similar to a ROM in concept except that ____________(a) It hasn’t capability to read only(b) It hasn’t capability to read or write operation(c) It doesn’t provide full decoding to the variables(d) It hasn’t capability to write onlyThe question was asked during an online exam.Question is from Programmable Array Logic topic in chapter Memory Devices of Digital Circuits
Answer» The CORRECT choice is (c) It doesn’t provide full decoding to the variables Easy explanation: A PLA is similar to a ROM in concept except that it doesn’t provide full decoding to the variables and doesn’t generate all the minterms as in the ROM. Programmable Logic Array is a type of FIXED ARCHITECTURE logic devices with programmable AND gates followed by programmable OR gates. It is a kind of PLD.

Discussion

42.	PLA contains ____________(a) AND and OR arrays(b) NAND and OR arrays(c) NOT and AND arrays(d) NOR and OR arraysI have been asked this question in final exam.This key question is from Programmable Array Logic topic in division Memory Devices of Digital Circuits
Answer» The correct OPTION is (a) AND and OR arrays The explanation is: PROGRAMMABLE Logic ARRAY is a type of fixed ARCHITECTURE logic devices with programmable AND gates FOLLOWED by programmable OR gates. It is a kind of PLD.

Discussion

43.	Outputs of the AND gate in PLD is known as ____________(a) Input lines(b) Output lines(c) Strobe lines(d) Control linesI got this question in unit test.Question is taken from Programmable Array Logic in portion Memory Devices of Digital Circuits
Answer» The CORRECT choice is (B) Output lines For EXPLANATION: Outputs of the AND gate in PLD is known as output lines.

Discussion

44.	PAL refers to ____________(a) Programmable Array Loaded(b) Programmable Logic Array(c) Programmable Array Logic(d) Programmable AND LogicI got this question during an interview for a job.My doubt is from Programmable Array Logic in chapter Memory Devices of Digital Circuits
Answer» CORRECT answer is (c) Programmable Array Logic Easiest explanation: PAL refers to Programmable Array Logic CONSISTING of programmable AND GATES and fixed OR gates.

Discussion

45.	The inputs in the PLD is given through ____________(a) NAND gates(b) OR gates(c) NOR gates(d) AND gatesI had been asked this question in an online quiz.I'd like to ask this question from Programmable Array Logic topic in division Memory Devices of Digital Circuits
Answer» The CORRECT CHOICE is (d) AND gates The explanation is: The inputs in the PLD is given through AND gate followed by inverting & non-inverting buffer. PLDs are PROGRAMMABLE Logic Devices consisting of logic gates, flip-flops and registers connected together on a single chip. THUS, it can be categorised into PROM, PAL and PLA.

Discussion

46.	PLA refers to _________(a) Programmable Loaded Array(b) Programmable Array Logic(c) Programmable Logic Array(d) Programmed Array LogicThis question was posed to me during an online interview.The question is from Programmable Logic Array in division Memory Devices of Digital Circuits
Answer» CORRECT CHOICE is (c) Programmable LOGIC ARRAY Explanation: PLA refers to Programmable Logic Array. It is a type of PLD having programmable AND and OR gates.

Discussion

47.	How many types of PLD is?(a) 2(b) 3(c) 4(d) 5I had been asked this question in an interview.Origin of the question is Programmable Logic Array topic in division Memory Devices of Digital Circuits
Answer» Right CHOICE is (a) 2 To explain I would SAY: There are two types of PLD, viz., devices with fixed ARCHITECTURE and devices with a flexible architecture. The main CATEGORIES of PLDs are PROM, PAL and PLA.

Discussion

48.	Why antifuses are implemented in a PLD?(a) To protect from high voltage(b) To increase the memory(c) To implement the programmes(d) As a switching devicesThis question was posed to me at a job interview.Origin of the question is Programmable Logic Array in chapter Memory Devices of Digital Circuits
Answer»

Discussion

49.	In PLD, there are provisions to perform interconnections of the gates internally, because of _________(a) High reliability(b) High conductivity(c) The desired logic implementation(d) The desired outputThis question was addressed to me during a job interview.The above asked question is from Programmable Logic Array topic in portion Memory Devices of Digital Circuits
Answer» The correct ANSWER is (c) The desired logic implementation For EXPLANATION: Programmable Logic Devices is a COLLECTION of a large number of gates, flip-flops, registers that are INTERCONNECTED on the chip. In PLD, there are provisions to perform interconnections of the gates internally so that the desired logic can be implemented.

Discussion

50.	Logic circuits can also be designed using _________(a) RAM(b) ROM(c) PLD(d) PLAThis question was posed to me in an internship interview.Question is from Programmable Logic Array in chapter Memory Devices of Digital Circuits
Answer» Correct answer is (c) PLD Explanation: PROGRAMMABLE Logic Devices is a collection of large number of gates, flip-flops, registers that are interconnected on the CHIP. Thus, it is USED for DESIGNING logic CIRCUITS.

Discussion

Explore topic-wise InterviewSolutions in .

In dynamic memory, CCD stands for __________(a) Charged Count Devices(b) Change Coupled Devices(c) Charge Coupled Devices(d) Charged Compact DiskThe question was asked during an interview.Origin of the question is Introduction of Memory Devices in portion Memory Devices of Digital Circuits

The example of dynamic memory is __________(a) CCD(b) Semiconductor dynamic RAM(c) Both CCD and semiconductor dynamic RAM(d) Floppy-DiskThe question was asked in an online quiz.This interesting question is from Introduction of Memory Devices in division Memory Devices of Digital Circuits

In an astable multivibrator, the amplifying elements are ____________(a) FET(b) JFET(c) OP-AMP(d) All of the MentionedThis question was posed to me during an interview.I want to ask this question from Multivibrators in chapter Memory Devices of Digital Circuits

Astable circuit acts as a/an ____________(a) Amplifier(b) Oscillator(c) Relaxation oscillator(d) MultiplexerI got this question during an online interview.I'd like to ask this question from Multivibrators topic in division Memory Devices of Digital Circuits

Bistable circuit is also known as ____________(a) Latch(b) Gate(c) Flip-flop(d) Bidirectional circuitThis question was addressed to me in unit test.My question is taken from Multivibrators in division Memory Devices of Digital Circuits

Bistable multivibrator is ________ in any state.(a) Stable(b) Unstable(c) Saturated(d) IndependentI got this question in an interview.I want to ask this question from Multivibrators topic in chapter Memory Devices of Digital Circuits

Monostable multivibrator is/has ________ state.(a) Stable(b) Unstable(c) One stable and another unstable(d) IndependentThe question was posed to me in an interview for job.Asked question is from Multivibrators topic in division Memory Devices of Digital Circuits

Astable multivibrator is ________ in any state.(a) Stable(b) Unstable(c) Saturated(d) Both Stable & SaturatedI have been asked this question in examination.My question is from Multivibrators topic in division Memory Devices of Digital Circuits

How many types of multivibrators are?(a) 2(b) 4(c) 5(d) 3I had been asked this question in my homework.My question comes from Multivibrators in portion Memory Devices of Digital Circuits

Multivibrators are characterized by ____________(a) Registers(b) Capacitors(c) Transistors(d) All of the MentionedI have been asked this question during an interview.This intriguing question comes from Multivibrators in section Memory Devices of Digital Circuits

A multivibrator is an electronic circuit used to implement ____________(a) Oscillator(b) Timer(c) Flip-flop(d) All of the MentionedI have been asked this question in an international level competition.Question is from Multivibrators in chapter Memory Devices of Digital Circuits

In a digital clock application, the basic frequency must be divided down as _____________(a) 1 Hz(b) 60 Hz(c) 100 Hz(d) 1000 HzI had been asked this question in exam.This intriguing question originated from Introduction to Hardware Description Language in portion Memory Devices of Digital Circuits

The use of VHDL can be done in _____ ways.(a) 2(b) 3(c) 4(d) 5The question was posed to me in class test.Question is taken from Introduction to Hardware Description Language topic in section Memory Devices of Digital Circuits

VHDL is being used for _____________(a) Documentation(b) Verification(c) Synthesis oflarge digital design(d) All of the MentionedThe question was asked in an interview for job.The question is from Introduction to Hardware Description Language topic in portion Memory Devices of Digital Circuits

Applications of PLAs are _____________(a) Registered PALs(b) Configurable PALs(c) PAL programming(d) All of the MentionedI got this question during an interview.The above asked question is from Programmable Array Logic in chapter Memory Devices of Digital Circuits

In FPGA, vertical and horizontal directions are separated by ____________(a) A line(b) A channel(c) A strobe(d) A flip-flopThis question was addressed to me during an interview for a job.Origin of the question is Programmable Array Logic in section Memory Devices of Digital Circuits

Which type of device FPGA are?(a) SLD(b) SROM(c) EPROM(d) PLDThe question was asked in an internship interview.I'm obligated to ask this question of Programmable Array Logic in division Memory Devices of Digital Circuits

For programmable logic functions, which type of PLD should be used?(a) PLA(b) PAL(c) CPLD(d) SLDThis question was posed to me in examination.The origin of the question is Programmable Array Logic in division Memory Devices of Digital Circuits

PLA contains ____________(a) AND and OR arrays(b) NAND and OR arrays(c) NOT and AND arrays(d) NOR and OR arraysI have been asked this question in final exam.This key question is from Programmable Array Logic topic in division Memory Devices of Digital Circuits

Outputs of the AND gate in PLD is known as ____________(a) Input lines(b) Output lines(c) Strobe lines(d) Control linesI got this question in unit test.Question is taken from Programmable Array Logic in portion Memory Devices of Digital Circuits

PAL refers to ____________(a) Programmable Array Loaded(b) Programmable Logic Array(c) Programmable Array Logic(d) Programmable AND LogicI got this question during an interview for a job.My doubt is from Programmable Array Logic in chapter Memory Devices of Digital Circuits

The inputs in the PLD is given through ____________(a) NAND gates(b) OR gates(c) NOR gates(d) AND gatesI had been asked this question in an online quiz.I'd like to ask this question from Programmable Array Logic topic in division Memory Devices of Digital Circuits

PLA refers to _________(a) Programmable Loaded Array(b) Programmable Array Logic(c) Programmable Logic Array(d) Programmed Array LogicThis question was posed to me during an online interview.The question is from Programmable Logic Array in division Memory Devices of Digital Circuits

How many types of PLD is?(a) 2(b) 3(c) 4(d) 5I had been asked this question in an interview.Origin of the question is Programmable Logic Array topic in division Memory Devices of Digital Circuits

Why antifuses are implemented in a PLD?(a) To protect from high voltage(b) To increase the memory(c) To implement the programmes(d) As a switching devicesThis question was posed to me at a job interview.Origin of the question is Programmable Logic Array in chapter Memory Devices of Digital Circuits

Logic circuits can also be designed using _________(a) RAM(b) ROM(c) PLD(d) PLAThis question was posed to me in an internship interview.Question is from Programmable Logic Array in chapter Memory Devices of Digital Circuits