The standard SRAM chips are costly as _________(a) They use highly advanced micro-electronic devices(b) They house 6 transistor per chip(c) They require specially designed PCB’s(d) None of the mentionedThis question was posed to me in an internship interview.I need to ask this question from Hierarchy of Memory in section Memory System of Computer Architecture

The standard SRAM chips are costly as _________(a) They use highly adv

1.	The standard SRAM chips are costly as _________(a) They use highly advanced micro-electronic devices(b) They house 6 transistor per chip(c) They require specially designed PCB’s(d) None of the mentionedThis question was posed to me in an internship interview.I need to ask this question from Hierarchy of Memory in section Memory System of Computer Architecture
Answer» The correct choice is (B) They HOUSE 6 TRANSISTOR per chip For explanation: As they require a large NUMBER of transistors, their COST per bit increases.

Discussion

No Comment Found

Related InterviewSolutions

The key factor/s in commercial success of a computer is/are ________(a) Performance(b) Cost(c) Speed(d) Both Performance and CostThis question was addressed to me in semester exam.Asked question is from Performance of Caches in chapter Memory System of Computer Architecture
What does the end instruction do?(a) It ends the generation of a signal(b) It ends the complete generation process(c) It starts a new instruction fetch cycle and resets the counter(d) It is used to shift the control to the processorI got this question in semester exam.My question is from Hardwired Control in portion Memory System of Computer Architecture
What does the hardwired control generator consist of?(a) Decoder/encoder(b) Condition codes(c) Control step counter(d) All of the mentionedI got this question in examination.This interesting question is from Hardwired Control in section Memory System of Computer Architecture
The general purpose registers are combined into a block called as ______(a) Register bank(b) Register Case(c) Register file(d) None of the mentionedI got this question in an online quiz.The query is from Multiple BUS Organistaion in chapter Memory System of Computer Architecture
There exists a separate block consisting of various units to decode an instruction.(a) True(b) FalseThe question was asked in unit test.Asked question is from Multiple BUS Organistaion topic in section Memory System of Computer Architecture
ANSI stands for _____________(a) American National Standards Institute(b) American National Standard Interface(c) American Network Standard Interfacing(d) American Network Security InterruptThis question was posed to me during an interview.This intriguing question comes from Single BUS Organisation in chapter Memory System of Computer Architecture
_________ signal enables the processor to wait for the memory operation to complete.(a) MFC(b) TLB(c) WMFC(d) ALBI have been asked this question during an online interview.This question is from Single BUS Organisation in portion Memory System of Computer Architecture
When two or more clock cycles are used to complete data transfer it is called as ________(a) Single phase clocking(b) Multi-phase clocking(c) Edge triggered clocking(d) None of the mentionedThe question was posed to me by my school teacher while I was bunking the class.I would like to ask this question from Single BUS Organisation in division Memory System of Computer Architecture
The registers, ALU and the interconnecting path together are called as ______(a) Control path(b) Flow path(c) Data path(d) None of the mentionedThe question was asked in unit test.The doubt is from Single BUS Organisation topic in division Memory System of Computer Architecture
The method of placing the heads and the discs in an air tight environment is also called as ______(a) RAID Arrays(b) ATP tech(c) Winchester technology(d) Fleming reductionI had been asked this question during an online exam.Question is taken from Secondary Storage topic in portion Memory System of Computer Architecture

Discussion

No Comment Found

Related InterviewSolutions

Reply to Comment