When an operand is stored in a register it is _______(a) Stored in the lower order bits of the register(b) Stored in the higher order bits of the register(c) Stored in any of the bits at random(d) None of the mentionedThis question was posed to me in exam.My query is from Motorola 680X0 Processor Architecture topic in section Processor Families of Computer Architecture

When an operand is stored in a register it is _______(a) Stored in the

1.	When an operand is stored in a register it is _______(a) Stored in the lower order bits of the register(b) Stored in the higher order bits of the register(c) Stored in any of the bits at random(d) None of the mentionedThis question was posed to me in exam.My query is from Motorola 680X0 Processor Architecture topic in section Processor Families of Computer Architecture
Answer» Correct option is (a) STORED in the LOWER order BITS of the register For explanation I would say: The DATA always GETS stored from the lower order to the higher order bits, except in the case of Little Endian architecture.

Discussion

No Comment Found

Related InterviewSolutions

.data directive is used _________(a) To indicate the ending of the data section(b) To indicate the beginning of the data section(c) To declare all the source operands(d) To Initialize the operandsThe question was posed to me in semester exam.I would like to ask this question from Intel IA-32 Pentium Architecture-2 in chapter Processor Families of Computer Architecture
The size of the floating registers can be extended upto _________(a) 128 bit(b) 256 bit(c) 80 bit(d) 64 bitThis question was posed to me by my school principal while I was bunking the class.My doubt is from Intel IA-32 Pentium Architecture-1 topic in section Processor Families of Computer Architecture
The __________ directive is used to allocate 4 bytes of memory.(a) DD(b) ALLOC(c) RESERVE(d) SPACEThis question was posed to me during an internship interview.Origin of the question is Intel IA-32 Pentium Architecture-2 in division Processor Families of Computer Architecture
The addressing method used in IA-32 is ____________(a) Little Endian(b) Big Endian(c) X-Little Endian(d) Both Little and Big EndianI have been asked this question by my college director while I was bunking the class.My doubt is from Intel IA-32 Pentium Architecture-1 topic in division Processor Families of Computer Architecture
The address system supported by ARM systems is/are ___________(a) Little Endian(b) Big Endian(c) X-Little Endian(d) Both Little & Big EndianI had been asked this question in examination.This intriguing question comes from ARM Architecture topic in division Processor Families of Computer Architecture
ARM stands for _____________(a) Advanced Rate Machines(b) Advanced RISC Machines(c) Artificial Running Machines(d) Aviary Running MachinesThis question was addressed to me during an interview.This question is from ARM Architecture topic in section Processor Families of Computer Architecture
The bit present in the op code, indicating which of the operands is the source is called as ________(a) SRC bit(b) Indirection bit(c) Direction bit(d) FRM bitI had been asked this question during an online interview.The origin of the question is Intel IA-32 Pentium Architecture-2 in chapter Processor Families of Computer Architecture
IOPL stands for ________(a) Input/Output Privilege level(b) Input Output Process Link(c) Internal Output Process Link(d) Internal Offset Privilege LevelI had been asked this question during an interview.This interesting question is from Intel IA-32 Pentium Architecture-1 in division Processor Families of Computer Architecture
The address space in ARM is ___________(a) 2^24(b) 2^64(c) 2^16(d) 2^32The question was posed to me by my school teacher while I was bunking the class.I'd like to ask this question from ARM Architecture topic in chapter Processor Families of Computer Architecture
The instructions in 68000 can deal with operands of three different sizes.(a) True(b) FalseI have been asked this question during an internship interview.My question is from Motarola 680X0 Processor Architecture in section Processor Families of Computer Architecture

Discussion

No Comment Found

Related InterviewSolutions

Reply to Comment