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The CORRECT ANSWER is (a) not GREATER than 0

To elaborate: The pinch off voltage for an N-channel JFET is NEGATIVE. The depletion region would extend into the N-channel if the reverse bias in the GATE to source voltage increases which means that the gate to source voltage has to be negative since the gate is N-type.

The correct option is (a) less than the INTERNAL pinch-off VOLTAGE

For explanation: Pinch-off would REQUIRE more voltage than the voltage required to ESTABLISH the p-n barrier voltage. This is evident from the dependence of such voltage on the doping concentration.

Correct option is (b) Increases

To explain: The INTERNAL PINCH off voltage is directly PROPORTIONAL to the CHANNEL thickness. If the channel thickness increases, the pinch off voltage increases.

Correct choice is (b) Increases linearly

To ELABORATE: The INTERNAL pinch-off voltage is linearly PROPORTIONAL to the DOPING concentration. Hence, it would increase with the increase in the doping concentration. The built-in-barrier potential is LOGARITHMICALLY proportional to the doping concentration of the gate.

Correct option is (c) Equal to the output current

For explanation I WOULD say: The cut-off FREQUENCY is an important FEATURE of the JFET due to the PRESENT of capacitive effects. It has been seen that the output current becomes a function of frequency in high-frequency applications and hence we have to choose a cut-off frequency so that the output current is equal to the input current.

The CORRECT ANSWER is (a) linearly related to the transconductance of the JFET

To elaborate: The cut-off frequency is seen to be linearly related to the transconductance of the JFET. This is typically DUE to the reactance of the CAPACITORS.

The correct OPTION is (b) Always OFF

The best explanation: The P-channel JFET doesn’t have a built-in channel for the flow of current. This is because the conduction in a P-channel JFET can begin after a certain voltage is applied at the gate which WOULD LEAD to WIDENING the channel between the source and the drain.

The correct answer is (a) Inversely PROPORTIONAL to the square root of the doping CONCENTRATION

The best explanation: The channel THICKNESS is inversely related to the square root of the doping concentration of the channel. This is because the ELECTRIC field developed is proportional to the channel doping concentration while the relation between the potential, electric field and doping concentration is VISIBLE from the Poisson’s equation.

The correct option is (C) 0.125 A

The explanation is: IDS = IDSS(1-VGS/VP)^2

When VGS = 0, IDSS = IDS = 5mA

When VGS = -6V, IDS = 5mA(1 + 4)^2

IDS = 5 X 25 = 125 mA.

Correct OPTION is (a) we can use either gate bias or a voltage divider bias circuit

The best explanation: To bias an e-MOSFET, we cannot use a self bias circuit because the gate to source voltage for such a circuit is ZERO. Thus, no channel is formed and without the channel, the MOSFET doesn’t work properly. If self bias circuit is used, then D-MOSFET can be operated in depletion MODE.

The CORRECT option is (a) RD < 6kΩ

Easiest explanation: In given circuit, VGS = -5V

VDS = VDD – IDSRD

To BIAS properly VDS > |VP| – |VGS|

VDS > -3

15 – 3mA*RD > -3

-3mA*RD > -18

RD < 6kΩ.

Right CHOICE is (c) 33V

The EXPLANATION: VDS = VDD – IDS(10k + 5k)

3 = VDD – 2(15)

3 = VDD – 30

VDD = 33 V.

Right OPTION is (C) 12.72V, 23.61mA

Explanation: IDS = [k’W/L(VGS – VT)^2]/2

VGS = 20 X 35/55 = 12.72 V

IDS = 0.25 (9.72)^2

IDS = 23.61 mA.

The CORRECT answer is (C) – 0.05mA

For explanation I would say: ISD = K’W(VSG – |VT|)^2/2L

ISD = 20*5*(-20-3)^2 = 52900μA = 0.05mA.

The correct option is (a) GM and rds

Explanation: The SMALL SIGNAL model of FET- MOSFET and JFET is obtained from the following equation IDS = gmVgs + Vds/rds

gm and rds are the small signal FET parameters.

The correct choice is (c) Transconductance increases linearly with IDS

The BEST explanation: Maximum transconductance OCCURS at VGS = 0, and it lies between 0-gmo. Transconductance decreases linearly with VGS according to equation gm = gmo(1-VGS/VP). However, gm ∝ \(\SQRT{I_{DS}}\), which is a parabolic increase, not LINEAR.

Right CHOICE is (B) 10mΩ^-1

Explanation: VP = -4V

gm = GMO (1 – VGS/VP) = 20 (1-2/4) = 20/2 = 10mΩ^-1.

The CORRECT option is (a) -2

For EXPLANATION I would SAY: AV = -gmRL’/1+gmRS

RL’= 15k|| 10k = 6kΩ

AV = – 2.

Correct ANSWER is (c) The output RESISTANCE decreases

To explain: For a CS AMPLIFIER without a bypass capacitor, the input resistance is unchanged and output resistance increase.

RI = RG for both.

RO = rds with bypass capacitor and rds = rds + (1+μ) RS without a bypass capacitor.

Output is still 180° out of phase COMPARED to applied input, but the GAIN decreases.

Right option is (b) CD amplifier

Explanation: For a CD amplifier, the gain AV = gm(RS||rds)/1+gm(RS||rds)

But since gm(RS||rds)>>1, gain AV≈1, that is, it acts as a voltage FOLLOWER. It is also CALLED a SOURCE follower.

Right choice is (a) 2500

Easy EXPLANATION: When the current SOURCE in small SIGNAL MODE, gmVGS is converted into a voltage source, the source is equal to μVGS where μ=gmrds is the amplification factor of the circuit.

Hence, amplification factor = 2500.

Right option is (a) ro1 / {(1/gm1 || RO2) + ro1}

For explanation I would say: M2 behaves as a Source follower i.e. it is being used in a C.D. configuration. M1 PROVIDES a output resistance of ro1but M2 provides an IMPEDANCE of (1/gm2||ro2). THUS, from the VOLTAGE gain of a follower stage, we conclude the overall voltage gain is ro1 / {(1/gm1 || ro2) + ro1}.

The correct option is (a) (1/gm2 || ro2) / {1/gm2 + ( 1/gm1 || ro1)}

The best I can explain: The voltage gain at NODE X is due to M1 being used in the CD configuration. SINCE M1 offers channel LENGTH modulation but not M2, we NOTE that the impedance looking into the source of M2 is 1/gm2 but for M1, it’s (1/gm2 || ro2). From the voltage gain of a FOLLOWER stage, we conclude that the voltage gain is (1/gm2 || ro2) / {1/gm1 + ( 1/gm1 || ro1)}.

The correct option is (d) (1/gm2 || ro2 || 1/gm1 || ro1)

The best explanation: The SOURCE of M1 and M2 are connected at NODE X. The impedance LOOKING into the source of a MOSFET is (1/gm || ro). If we look at node X, M1 and M2 are connected from Node X to ground. Hence, they are parallel to each other and the OVERALL impedance becomes (1/gm2 || ro2 || 1/gm1 || ro1).

The CORRECT CHOICE is (a) 32.6

To explain I would SAY: The voltage gain is given by RL/(1/gm + RL) where RL is the 50 Ω load. Now, we SEE that if the voltage gain is .25, gm is 1/175. Now, gm is \(\SQRT{(2* µ_nC_{ox} * (W/L) * Id)}\) where (W/L) is the aspect ratio, Id is the drain current. We have all the values and the aspect ratio becomes 32.6.

Correct option is (c) Depends on it’s transconductance and low

Explanation: The output IMPEDANCE of the follower is a function of the transconductance. But it’s ALSO a function of the channel length modulation. But the RESISTANCE offered due to channel length modulation is much greater than the inverse of the transconductance. It can be CONCLUDED that the output of the follower depends on the transconductance and it’s low.

Correct answer is (B) Buffer stage

Easiest explanation: The C.D. configuration offers high input impedance to the input SIGNAL and low output impedance while SENSING the output signal. THUS, it is used as a buffer stage.

Right option is (a) 50 Ω

For EXPLANATION I would say: Since the transconductance is .02, it’s INVERSE is 50. From the general expression of voltage gain of a source follower, we conclude that the LOAD should be 50 Ω since the inverse of the transconductance is the IMPEDANCE LOOKING into the source of the MOSFET. For maximum power transfer, we have to match both the impedance.

The correct option is (a) R / ((1/g || r ) + R) * g *R * R / (1/g + R)

To explain I would say: This is a cascade of a follower stage follower by a CS stage which precedes another follower stage. The gain due to each stage gets MULTIPLIED until we reach the output. For the first stage, the gain is R/ ((1/g || r)+ R) since M1 has CHANNEL length modulation. The second stage has a gain of g * R while the final stage has a gain of R/ (1/g + R). After MULTIPLYING the gains, we get R/ ((1/g || r )+ R) * g *R * R/ (1/g + R).

Correct answer is (b) R/ ((1/g + R) * g * (R || r) * R/ ((1/g || r) + R)

Explanation: This is a CASCADE of a follower stage follower by a CS stage which precedes another follower stage. The GAIN due to each stage gets multiplied until we reach the output. For the first stage, the gain is R / ((1/g+ R). The second stage has a gain of g * (R || r)while the final stage has a gain of R/ ((1/g || r) + R)- the effect of r is simply due to CHANNEL length modulation. After multiplying the GAINS, we get R/ ((1/g + R) * g * (R || r) * R/ ((1/g || r) + R).

Correct option is (a) R / ((1/g || r) + R) * g * R * R / ((1/gm || r))

The BEST I can explain: This is a cascade of a FOLLOWER stage follower by a CS stage which precedes another follower stage. The gain due to each stage gets multiplied until we REACH the OUTPUT. For the first stage, the gain is R/ ((1/g || r) + R). The second stage has a gain of g * R while the final stage has a gain of R/ ((1/g || r) + R). The presence of r is due to channel length modulation. After multiplying the gains, we GET R/ ((1/g || r) + R) * g * R * R / ((1/gm || r)).

The correct choice is (b) INCREASES

The best I can explain: The gain of the follower stage is given by Rs/(1/GM + Rs). Hence, we READILY conclude that if the TRANSCONDUCTANCE (gm) increases, the gain will increase.

Right ANSWER is (a) increase

Easy explanation: The square root of the aspect RATIO is directly proportional to the transconductance of the MOSFET. If it increases, the transconductance increases and hence according to the EXPRESSION of the voltage gain of a follower STAGE gain increases.

Correct choice is (a) (1/g || r) / (1/g + (1/g || r))

EXPLANATION: The voltage gai at node X will be due to the follower stage. SINCE M2 has CHANNEL length modulation, we observe that the total resistance at the source of M2 is (1/g || r). Thus, from the expression of voltage gain of a follower- the voltage gain at node x is (1/g || r) / (1/g + (1/g || r)).

Right choice is (c) {(1 + gr)* (R || 1/g || r) + (R || 1/g || r)} || R

Best explanation: The DRAIN of M2 offers a resistance of {(1 + gr)* (R || 1/g || r) + (R || 1/g || r) due to channel length modulation and the degeneration resistance R || 1/g || r connected to the drain of M2. This comes in parallel to R connected to the SOURCE of M2. Hence the OVERALL resistance becomes {(1 + gr)* (R || 1/g || r) + (R || 1/g || r).

Correct choice is (a) G * {(1 + GR)* (R || 1/g || r) + (R || 1/g || r)} || R

The explanation is: The voltage gain for M2 will be due to a CG stage. M2 has CHANNEL length modulation and is degenerated by (R || 1/g || r). Thus the output IMPEDANCE rises to {(1 + gr)* (R || 1/g || r) + (R || 1/g || r)} ||R and hence the gain for only M2 is g * {(1 + gr)* (R || 1/g || r) + (R || 1/g || r)} || R.

Right answer is (d) {(R || 1/g || r) / (1/g + (R || 1/g || r)} * g * [{(1 + gr)* (R || 1/g || r)+ (R || 1/g || r)} ||R] * R / {(1/g || r) + R

To explain I would say: This is a cascade of a FOLLOWER stage preceding a CG stage which is FOLLOWED by another CD stage. The VOLTAGE gain due to first stage is {(R || 1/g || r) / (1/g + (R || 1/g || r)} since the source of M1 is connected to the source of M2 which offers a RESISTANCE of (1/g || r). The voltage gain of the next stage is due to the CG stage degenerated by (R || 1/g || r)} and the gain is g * [{(1 + gr)* (R || 1/g || r)+ (R || 1/g || r)} || R]. Finally, the last stage offers a voltage gain of R / {(1/g || r) + R. After multiplying all these gains, we have the overall voltage gain as {(R || 1/g || r) / (1/g + (R || 1/g ||r)} * [g * {(1 + gr)* (R || 1/g || r)+ (R || 1/g || r)} ||R] * R / {(1/g || r) + R.

The CORRECT answer is (B) No

Best explanation: The voltage gain of the follower STAGE READILY tells US that it can never be used as an amplifier. It can only be used as a buffer.