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The correct CHOICE is (B) No

For explanation I would say: From the expression of voltage GAIN, we find that if the voltage gain is 1, the transconductance has to be infinite which is practically IMPOSSIBLE. However, we can reach a voltage gain of approximately equal to 1 but NEVER equal to 1.

Right CHOICE is (a) True

The explanation: The OUTPUT impedance of a CS stage will increase HIGHLY DUE to degeneration. Hence, it’ll be always more than that of a follower.

The correct OPTION is (a) GREATER

To explain I would say: The input to a follower stage is at the gate of the MOSFET while for a CG stage, it’s at the source of the MOSFET. Hence, the input IMPEDANCE of a follower will be very MUCH greater than that of a CG stage.

Correct choice is (a) \(\frac{1}{2}\)µnCox*(W/L)(V1-Vth)

To elaborate: The transconductance is the ratio of a small CHANGE in the output CURRENT DUE to a small change in the input voltage. By differentiating the equation relating the current to the input voltage of a MOSFET with RESPECT to the input voltage, we’ll get \(\frac{1}{2}\)µnCox*(W/L)(V1-Vth).

The correct option is (d) R1 || ro

Easy explanation: To find the output impedance, we perform a small signal analysis with the help of our rπ model. After PLACING every voltage source (VCC and V1) to ground, we connect a simple voltage source at the DRAIN node. Thereafter, the ratio of applied voltage to input current gives us the impedance looking into the drain which is ro. But this voltage will be applied in PARALLEL to R1. Hence the total output impedance is R1 || ro.

Right CHOICE is (a) Infinite

For explanation: The input impedance of the C.S. stage, i.e. the impedance looking into the gate of M1 is always infinite. HENCE, in presence of early EFFECT, the input impedance REMAINS infinite.

Right answer is (c) R1

To explain: If the EARLY effect is NEGLECTED, ro –> ∞ and hence, the output impedance is only R1. This is inferred by PERFORMING the small SIGNAL analysis at the output node or the drain of the M1.

The CORRECT answer is (c) gm * R1||ro

Explanation: This is easily observable by performing a small signal analysis at the output of the C.S. stage. We need to turn off all voltage SOURCES, Vcc mainly, and GIVE a small INPUT at the GATE. Thereby, the voltage gain becomes gm * R1||ro. The presence of early effect reduces the gain a bit and deviates M1 from its ideal characteristics.

Correct answer is (a) A DEGENERATED C.S. stage

The best I can explain: The above SHOWN stage is a degenerated CS stage. This stage is called so because the current source connected at the source of M1 reduces the TOTAL gain of the CS stage. The current source provides a finite output impedance which is connected the source. Thereby, the overall gain decreases.

The correct option is (a) (1 + gm * (R1 || R2)) * Ri + (R1 || R2)

For explanation: We calculate the OUTPUT impedance by shorting the two VOLTAGE sources to ground. Thereafter, as we apply a simple step input at the output node, i.e. the COLLECTOR node, we’ll FIND that the total impedance at connected to the DRAIN of M1 is nothing but (1 + gm * (R1 || R2)) * Ri + (R1 || R2) where gm is the transconductance of M1, R1 || R2 is the total resistance connected at the drain and Ri is the total resistance connected at the source. The output impedance would’ve been R1 || R2 if the current source was absent.

Right answer is (a) R3

Easiest explanation: By PERFORMING a simple SMALL SIGNAL ANALYSIS, we find that the input resistance is simply R3. The impedance is not infinite since we have a resistor between the gate and the input voltage.

Right option is (B) 1.25

Best explanation: The voltage gain for a DEGENERATED CS stage is \(\frac{-Rd}{(\frac{1}{gm} + Rs)}\). Hence, after putting the values, we GET 5/4 and hence the ANSWER becomes 1.25. Rd is the total resistance connected to the drain of the M1 while Rs is the total resistance connected to the source of the M1.

The correct answer is (c) Vcc– R1* µn Cox(W/L) * (V1-Vth)^2

For explanation I would SAY: SINCE M1 and M2 receive the same bias voltage V1, the current generated by both the MOSFET’s are same i.e. \(\frac{1}{2}\)µn Cox(W/L) * (V1-Vth)^2. Both the currents enter node S and hence the voltage at node S is VccR1* \(\frac{1}{2}\)µn Cox(W/L) * (V1-Vth)^2.

Correct answer is (a) R1 || ro1 || ro2

Easiest explanation: If we perform a small signal ANALYSIS at node S, we will find that three resistors are connected from node S to ground. They are R1, and the resistances appearing between source and DRAIN of the MOSFET’s DUE to channel length MODULATION ie ro1 and ro2. Hence, the output resistance is R1 || ro1 || ro2.

Right option is (b) The voltage GAIN remains the same

Easiest explanation: The dependent current source has a variable resistance. If K doubles, the magnitude of current provided by the current source doubles, and thus, the total resistance connected to the source of M1 reduces by 2. By using the expression of voltage gain,\(\frac{-Rd}{(\frac{1}{gm} + RS)}\), we find that a decrease in Rs leads to an INCREASE in the voltage gain.

Right answer is (a) (1 + (gm * ro)) * Rs + ro

Explanation: By PERFORMING a small signal analysis of the FOLLOWING CIRCUIT, we find that the output impedance of the circuit is simply (1 + (gm * ro)) * Rs + ro. For doing this analysis, we have to short V1 and V2 to ground. Thereafter, we place a voltage source at the input NODE and measure current. The impedance measured will be the output impedance which is (1 + (gm * ro)) * Rs + ro.

Correct option is (a) R4

To explain I would say: The output impedance is CALCULATED by a SIMPLE SMALL signal analysis. We set Vcc and V1 to 0 and PLACE a voltage source at the output node. We find that only R4 is the output impedance. Note that even if R2 seems to be connected to R4, it doesn’t AFFECT the output impedance since during small signal analysis, the node where R2 and R4 meets, is set to ground.

The CORRECT choice is (a) R2 || R3

To explain: The input impedance can be calculated by performing a small SIGNAL analysis at the input side IE the Gate of M1. We need to set Vcc and V1 to 0 and place a voltage source at the node after R1. Henceforth we find that R2 and R3 are simply connected from the same node to ground so they are parallel to each other. Note that by input impedance of the C.S. stage, we REFER to the impedance seen by the signal after it CROSSES R1.

The CORRECT OPTION is (d) V1 * [(R2 || R3) / {R1 + (R2 ||R3}]

For explanation I would say: The Thevenin resistance seen by the input voltage V1 is R1 + (R2 || R3). The Thevenin resistance is calculated by setting Vcc to 0 and hence calculating the current entering the C.S. STAGE. After finding the Thevenin Resistance, it is found that the voltage drop across the gate of M1 is due to a potential DIVIDER between R1 and (R2 || R3) where the voltage across (R2 || R3) is TRULY the gate voltage. Hence, the total gate voltage V1 is attenuated and becomes V1 * [(R2 || R3) / {R1 + (R2 ||R3}] .

The correct option is (a) It increases

The explanation: This is a fact DERIVED by performing the small signal analysis of a DEGENERATED C.S. stage. The output impedance increases if we degenerate the MOSFET and this further increases the linearity of OPERATION.

Right answer is (a) R1 = 1k, R2 = 2k, R3 = 3k

The best EXPLANATION: The Thevenin resistance SEEN by V1 is R1 + (R2 || R3). The gate voltage is a result of V1 going through a potential divider of R1 and (R2 || R3) where the voltage ACROSS (R2 || R3) is essentially the gate voltage ie V1 * [(R2 || R3) / { R1 || R2 || R3) }]. Hence, we need to maximize (R2 || R3) which is possible if R2=2k and R3=3k. This implies R1 has to be equal to 1k.

The correct choice is (a) 4.7 V

Explanation: Firstly, we know that the voltage GAIN from the gate to the source is gm * R4. We observe that Vg is Vin * [(R2 || R3) / {R1 || R2 || R3}, where Vin is 1v and the values of R1, R2 and R3 are provided, which is roughly equal to .55V. This .55V is getting amplified by a factor of gm*R4. Now, Vout is related to Id, the drain CURRENT, as Vdd – Id*R4. Again, we know that gm = 2Id/Vgs-Vth. So, we have 2 equations as FOLLOWS:

i. Vout = gm*R4 = 2*Id/(Vgs – Vth)*R4

ii. Vout = Vdd – Id * R4

We have the values of all the parameters. Solving for Vout will YIELD Vout as 4.7V.

Correct choice is (b) False

Best explanation: Capacitors always block D.C. SIGNALS. In fact, they provide A.C. COUPLING to ensure that the BIASING of consecutive stages of transistors do not GET affected by the individual biased conditions.

The CORRECT ANSWER is (a) 5 V

Explanation: There is no RESISTOR PLACED between the drain and the supply voltage, Vdd. Hence, Vout is nothing but 5V.

Right choice is (d) (R2 || R3 || R4) * K * (V1 – Vth)

The explanation is: Ideally, the bypass capacitor would short the source TERMINAL of the M1 to GROUND. Hence, this becomes a simple C.S. stage instead of a degenerated C.S. stage. Hence, the gain is simply GM*(total resistance connected at the drain). The total resistance connected at the drain is (R2 || R3 || R4) since all the three resistors are parallel to each other. The transconductance(gm) is K(V1-Vth). Hence the overall voltage gain is (R2 || R3 || R4) * K * (V1 – Vth).

The correct OPTION is (d) gm * Rd * {Rs / (Rs + 1/gm)}

Easiest EXPLANATION: The voltage gain from the source of M1 to the drain of M1 can be found out from a SMALL signal analysis and it’ll turn out to be gm * Rd. But the input voltage is a result of the potential divider between Rs and 1/gm. Hence, the overall voltage gain is gm * Rd * {Rs/ (Rs + 1/gm)}.

Correct answer is (c) Rs || 1/gm

For explanation: The input IMPEDANCE can be calculated by performing a SMALL SIGNAL analysis at the input node. We need to set Vg and Vdd to 0V and apply a small input voltage at the source. Now, the impedance looking into the source is 1/gm and Rs is parallel to this impedance. Hence, the TOTAL input impedance is Rs || 1/gm.

Correct answer is (a) GM * Rd

To explain: In absence of channel LENGTH MODULATION, ro=0. The gain is simply gm * Rd. It should be noted that the CG stage doesn’t INVERT and hence the voltage gain is not -gm * Rd.

Right option is (b) Rd || ro

For explanation I would say: In presence of CHANNEL LENGTH modulation, ro APPEARS to be in parallel to Rd. Hence, the total output impedance BECOMES Rd || ro. In the ABSENCE of channel length modulation, the output impedance is Rd only.

Correct option is (a) Rd || {Rs*(1+gm * RO) + ro}

EASY explanation: The impedance LOOKING into the drain of M1 would be similar to that of a CS stage with source degeneration. That implies the impedance isRs*(1+gm * ro) + ro. But this impedance is parallel to Rd. Hence, the OVERALL output impedance becomes Rd || {Rs*(1+gm* ro) + ro}.

Correct option is (b) unity

Easy EXPLANATION: The input to a CS stage is at the SOURCE of M1. This current simply flows into the channel and flows out of M1. Approximately, we can say that the overall current gain is unity since the gain CONTRIBUTES very low current.

Right answer is (C) – {gm1 * (Rd || ro1) * gm2 * (Rd1 || ro2)}

Explanation: This is a cascade of a CG stage preceding a CS stage. For the CG stage, the voltage gain is gm * (Rd || ro1). But after this stage, the signal gets AMPLIFIED by the CS stage with a factor of – {gm2 * (Rd1 || ro2)}. Hence, the overall voltage gain is the product of both the factors i.e. – {gm1 * (Rd || ro1) * gm2 * (Rd1 || ro2)}. Note that the input impedance looking into M2 is infinite ad hence the voltage gain of the CG stage is TYPICALLY unaffected by the CS stage (for LOW frequency operations only).

Correct answer is (a) True

The best I can explain: The VOLTAGE gain of a FOLLOWER is always less than that of a CG STAGE. This can be proven by a small signal analysis that the voltage gain for a follower is RS/(1/gm + Rs) while that of the CG stage is gm * Rd. HENCE the above statement is true.

Right answer is (a) – {gm1 * (Rd || 1/gm2) * (Rd1/ (1/gm2 + Rd))}

Explanation: This is a cascade of CS stage PRECEDING a CG stage. The voltage gain of the first stage is – (gm1 * Rd || 1/gm2). This is because the drain of M1 is connected to the SOURCE of M2 and the IMPEDANCE looking into the source of M2 is 1/gm2. Now, the source of the CG stage is connected to Rd and hence the voltage gain due to this stage is AFFECTED by source degeneration and the voltage gain is Rd1/ (1/gm2 + Rd). The overall voltage gain is – {gm1 * (Rd || 1/gm2) * (Rd1/ (1/gm2 + Rd))}.

Right choice is (c) About 4K

To ELABORATE: The voltage gain is GIVEN by gmRd. So, gm BECOME 2mS and a resistance of 4k Ω will be NECESSARY.

The correct choice is (a) True

To explain I would say: The input CURRENT flows through the source of the MOSFET while the gate current is NEARLY equal to 0. HENCE, the ENTIRE current coming out of the drain is due to the source current.

Right answer is (a) gm || 1/ro

To explain: The input impedance can be found by performing a small SIGNAL ANALYSIS at the input NODE i.e. source of the MOSFET. Due to channel length modulation, the effect of ro would make the input impedance gm || 1/ro.

Correct choice is (B) Rd || RO1 || 1/gm2 || ro2

To explain: We develop a Thevenin’s equivalent w.r.t. node X and ground. But this is LENGTHY process. But then again, we can use the process as follows. For Thevenising, firstly we set Vdd and VIN to ground. Thereafter, we see that Rd and ro1 are in parallel to each other since they are connected from node X to ground. Next, we see that the impedance provided by M2 is 1/gm2 || ro2 but it again occurs from Node x to ground. Hence, all the impedances are parallel to each other and the total impedance at node X is Rd || ro1 || 1/gm2 || ro2.

Correct choice is (d) gm1 * Rd || 1/GM2 || ro2 * gm2 * Rd2

Easy explanation: The VOLTAGE GAIN DUE to M1 is gm1 * Rd || 1/gm2 || ro2 since we find that the drain of M1 is connected to the source of M2 and the impedance looking into the source of a MOSFET is 1/gm2 || ro2 due to the channel length modulation of M2. Now, the voltage gain due to the 2^nd CG STAGE is simply gm2*Rd2. Hence, the total voltage gain is a product of both the factors ie gm1 * Rd || 1/gm2 * gm2 * Rd2.

Right choice is (d) – gm1 * rd1 * gm2 * RD2

The best explanation: The voltage gain for the C.G. stage is SIMPLY gm * Rd1. The voltage gain of the next stage is – gm * Rd2. Note that, the ideal current source exhibits INFINITE OUTPUT impedance and doesn’t AFFECT but only increases the linearity of operation.